Advanced Micro Devices Corporation

Digital Equipment Corporation

Intergraph Corporation

Altera Corporation

Hamid Partovi

Donald A Draper

Steven W Butler

Frederick Daniel Weber

Robert C Burd

Udin Salim

Chun Jiang

Luigi Di Gregorio

Minh Van Ngo

Angela Tai Hui

Steven C Avanzino

Matthew P Crowley

Kaizad R Mistry

David Benjamin Krakauer

Rajesh Khanna

Michael A Case

Michael Allen Van Buskirk

William Ralph Wheeler

John Christian Holst

Dennis L Wendell

Amos Ben-Meir

Michael L Golden

Ronald F Talaga, Jr

Bill Yowjuang Liu

Luigi DiGregorio

Yi-Ren Warry Hwang

Michael Leary

Laun Q Tran

Luan Tran

William A McGee

John Ngai

Steven G Lloyd

John Yong

Andrew J Barber

The capacitance between the gate of a transistor and local interconnect is reduced employing SiC as an etch stop layer. Embodiments include depositing a SiC etch stop layer having a thickness of about 500-1000 &angst; and a dielectric constant of less than about 3.2, thereby providing a composite dielectric constant between the gate and local interconnect of between about 3.7 to about 4.7. The SiC etch stop layer can be deposited by PECVD or HDP techniques.

Interconnect methodology employing a low dielectric constant etch stop layer

Air gap insulation regions are formed selectively within high parasitic capacitance regions in which conductive lines are closely proximate and generates an intolerable amount of parasitic capacitance. The selective formation of air gap insulation regions improves circuit performance by reducing the parasitic capacitance and device reliability by reducing the stress fracture problem of conventional air gap insulation schemes.

Selective air gap insulation

A flip-flop circuit includes a differential stage coupled to a transparent latch. Respective sides of the differential stage, referred to as the &ldquo;output side&rdquo; and the &ldquo;reference side,&rdquo; are precharged high during a precharge phase. During an evaluation phase, the state of a data input signal is sensed. Depending upon the state of the data input signal, either the output side or the reference side is discharged. Also, during the evaluation phase, the transparent latch is enabled, and thereby samples and stores an output signal from the output side of the differential stage. Upon initiation of the next precharge phase, the transparent latch is quickly disabled (i.e., is placed in an opaque state), and retains its present state. Since only a single side of the differential stage is used to drive the transparent latch, the differential stage may advantageously be implemented in an asymmetric fashion. In yet an additional embodiment, complex logic may be added to the differential stage of the flip-flop circuit.

Low-power flip-flop circuit employing an asymmetric differential stage

The capacitance between a gate electrode of a transistor and local interconnect is reduced by employing SiC sidewall spacers on the side surfaces of the gate electrode when forming the source/drain regions with shallow extensions. Embodiments include forming SiC sidewall spacers at a width of about 500 .ANG. to about 800 .ANG. having a dielectric constant of less than about 3.2, depositing a silicon oxide inter-dielectric layer, and forming the local interconnect through the inter-dielectric layer. The resulting composite dielectric constant between the gate electrode and local interconnect is about 4.2 to about 4.7.

Method to reduce gate-to-local interconnect capacitance using a low

A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an 'implicit' one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

Dynamic latch circuitry

A NOR gate pair includes a first and second NOR gate, each with a plurality of inputs and an output. A first NAND gate has a first input coupled to the output of the first NOR gate, a second input coupled to the output of the second NOR gate through a first input inverter, and an output. A second NAND gate has a first input coupled to the output of the second NOR gate, a second input coupled to the output of the first NOR gate through a second input inverter, and an output. A first output inverter is coupled to the output of the first NAND gate and a second output inverter is coupled to the output of the second NAND gate. This configuration assures that NOR gates used in a one-hot-decode decoder will all have logic-low outputs during a precharge phase.

Dynamic NOR gates for NAND decode

A circuit which protects an integrated circuit (IC) device from damage due to electrostatic discharge (ESD). The protection circuit includes an N-channel metal oxide semiconductor field effect transistor (MOSFET) clamping device and a gate modulation circuit. The source and drain of the MOSFET clamp are connected between an input/output (I/O) pad of the IC and a ground reference voltage. During normal operation of the IC, the gate modulation circuit disables the MOSFET clamp by connecting its gate terminal to a ground reference voltage. This permits signal voltages to pass between the I/O pad and any operating circuits connected to the pad. During an ESD event, the gate modulation circuit connects the gate to the I/O pad, which enables the MOSFET clamp, causing any ESD voltages and resulting currents to be shunted through the MOSFET clamp to ground. As a result, the ESD clamp reaches its clamped-to snapback voltage via an increase in MOSFET channel current, and not via junction breakdown. This insures that the ESD clamp reaches its snapback voltage before the onset of junction breakdown in the operating circuits. The circuit is especially useful in integrated circuits where the gate oxide of a standard ESD clamp transistor is too thin to protect the operating logic from I/O signal voltages that are greater than the supply voltage used for the operating logic circuits.

Electro-static discharge protection device having a modulated control

A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an 'implicit' one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

Latching method

A current-sensing static amplifier-based flip-flop is useful for high-performance VLSI circuitry. The flip-flop has a short latency and a small hold time, advantageous features in high-performance microprocessors. A flip-flop circuit includes an amplifier stage and a static stage. The amplifier stage has a data input terminal and a clock input terminal. The amplifier stage includes a dual-output amplifier having two output lines connected respectively to two current pulldown paths and a gate connected between the current pulldown paths. The static stage is connected to the amplifier stage and including a static latch.

Amplifier-based flip-flop elements

An output buffer with improved tolerance to overvoltage conditions. Among other features, especially when in a high-impedance state, the output buffer prevents a leakage path from a pad (108) through a pull-up driver (101) to supply voltage VDD when any voltage above VDD is placed on the pad (108). Further, the output buffer provides improved transient response characteristics. In one embodiment, the output buffer includes a pull-up driver (101), a first tracking transistor (120), a second tracking transistor (122), a voltage bias generator (112), and a coupling capacitor (124).

Output buffer with improved tolerance to overvoltage

A Self-Timed Pulse Control circuit and operating method is highly useful for adjusting delays of timing circuits to prevent logic races. In an illustrative example, the STPC circuit is used to adjust timing in self-timed sense amplifiers. The Self-Timed Pulse Control (STPC) circuit is integrated onto an integrated circuit chip along with the circuit structures that are timed using timing structures that are adjusted using STPC. The STPC is also advantageously used to modify the duty cycle of clocks, determine critical timing paths so that overall circuit speed is optimized, and adjusting dynamic circuit timing so that inoperable circuits become useful.

Self-timed pulse control circuit

A phase-frequency detector provides a decreased blind spot near 360.degree. of phase error and a resulting increased phase error detection range. In one embodiment, the phase-frequency detector includes two latches that are set in response to the detection of positive transitions in respective input clock signals. A reset controller resets both latches when they both get set. The duration and sequence of the latch states are thereby indicative of phase errors between the input clock signals. Two edge-triggered pulse generators provide a sustained indication of a detected positive transition in the respective input clock signals. When the time duration of the sustained indications is set equal to the reset time required by the latches and reset controller, the blind spot of the phase-frequency detector is largely eliminated.

Phase frequency detector having reduced blind spot

A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an 'implicit' one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially setup and clock-to-output times. The flip-flop consumes no static power.

Latching methodology

Dynamic latching device

An ESD protection device is provided which includes a self referencing modulation circuit for controlling its operation. The modulation circuit includes a diode stack coupled to a resistor and further coupled to an inverter powered by the signal pad voltage in one embodiment, or an odd plurality of series connected inverters powered by the signal pad voltage in an alternate embodiment. The inverter chain is coupled to the ESD clamp. The modulation circuit requires no reference supply voltage to operate. The ESD protection circuit shunts currents associated with ESD events away from ICs as well as clamping I/O pad voltages to acceptable levels during an ESD event.

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Sunnyvale, CA, United States of America

Hamid Partovi