Motorola Corporation

Innovative Silicon Isi Sa

Hamid Daghighian

Gregory Allan Popoff

Paul De Champs

There are many inventions described herein as well as many aspects and embodiments of those inventions, for example, circuitry and techniques for reading, writing and/or operating semiconductor memory cells of a memory cell array, including, for example, electrically floating body transistors in which an electrical charge is stored in the body of the transistor. In one aspect, the present inventions are directed to one or more independently controllable parameters of a memory operation (e.g., restore, write, refresh), to program or write a data state into a memory cell. In one embodiment, the parameter is the amount of time of programming or writing a predetermined data state into a memory cell. In another embodiment, the controllable parameter is the amplitude of the voltage of the control signals applied to the gate, drain region and/or source region during programming or writing a predetermined data state into a memory cell. Indeed, the controllable parameters may be both temporal and voltage amplitude. Notably, the memory cell array may comprise a portion of an integrated circuit device, for example, logic device (e.g., a microprocessor) or a portion of a memory device (e.g., a discrete memory).

Method and apparatus for varying the programming duration and/or voltage of an electrically floating body transistor, and memory cell array implementing same

A D/A/ converter for use in a microprocessor comprises first and second timers (3A, 3B), first and second modulus latches (2A, 2B) associated respectively with said first and second timers for holding respective digital values, the timers being arranged to produce first and second respective overflow signals (4A, 4B) at predetermined counts, wherein said second overflow signal (4B) causes said first and second timers (3A, 3B) to be reset to the digital values held in said respective latches (2A, 2B), and bistable means (6) for receiving said overflow signals and producing an output at a first level in response to said first overflow signal and at a second level in response to said second overflow signal, whereby the pulses so produced form a pulse width modulated signal whose duty cycle is representative of the ratio of said respective digital values held in said respective latches.

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Geneva, Switzerland

Hamid Daghighian