International Business Machines Corporation

Haluk O Askin

Guy Rabbat

Frank David Ferraiolo

David T Hui

Joseph R Cavaliere

Charles B Winn

John Balyoz

George Sonoda

Bijan Salimi

James M Lee

Edward C Jacobson

Bryant K Ho

Achilles A Sarris

Doyle E Beaty, Jr

An improved differential cascode current push-pull driver is provided by controlling the up level by clamping the collector node with respect to output signal reference VR to less than VCC. The collector resistors are made smaller so there is smaller signal swing and faster operation.

Fast limited swing push-pull driver

A circuit for converting a multi-bit data signal from a first format to a second format. The circuit includes an input for receiving the multi-bit data signal in a first format, an output for providing the multi-bit data signal in a second format, and a ring counter having a number of stages for providing, in sequential order, stage output signals. A format conversion device connected between the input and the output has a number of latches with each latch being connected to the input for simultaneously receiving data bits of the multi-bit data signal in the first format. A control circuit is provided for controlling the latching of selected data bits in each of the latches, and a transmission circuit is provided between the latches and the output for transmitting the bits latched in the latches to the output responsive to the stage output signals of the ring counter, thereby placing the multi-bit data signal in the second format.

Circuit for converting between serial and parallel data streams by high

A very large scale multicell integrated circuit is provided with significantly improved circuit density. Both active and passive circuit elements are formed in a semiconductor substrate using ordinary diffusion techniques. Connectors, preferably made of polysilicon material, are then formed on the surface of the substrate. The connectors have bonding pad areas located along predetermined lines where metal connectors of later-formed metallization layers can be located. Some of the connectors have bonding pad areas connected to circuit elements while others are left unconnected. The subsequently formed metallization layers can then be used to connect together various ones of the circuit elements and multiple ones of the cells together in any desired circuit configuration using the polysilicon connectors.

VLSI integrated circuit having parallel bonding areas

A communication circuit for transmitting multi-bit digital signals from one integrated circuit to another upon a single conductor utilizing a multi-level analog signal. The transmitting circuitry includes first through third drivers, only one of which is activated at any one time. The collector of an output transistor of a first of the drivers is coupled directly to the single bus conductor, the collector of an output transistor of the second driver is coupled to the bus through a single transistor, and the collector of an output transistor of the third driver is coupled to the bus through two series-connected diodes. The receiving circuitry is composed of three receivers, each including an input and output transistor pair coupled in a Darlington configuration. The base of the input transistor of the first receiver is coupled to the bus through a single diode connected in a first direction, the second receiver coupled to the input bus through a diode in a direction opposite the first direction, and the third receiver is coupled to the input bus via two series-connected diodes, this arrangement of diodes providing three different threshold voltage levels. The outputs of the three receivers are combined to yield an output digital signal which corresponds to the input digital signal.

Multi-level communication circuitry for communicating digital signals

Disclosed is a field effect transistor (FET) memory array in which each of the cells forming the array comprises four FET's. The first and second of the four FET devices are cross-coupled while the third and fourth FET devices form loads for the cross coupled pair. D.C. stability is achieved by conditioning the load FET devices into partial conduction during the stand-by state of the memory cell.

D. C. Stable semiconductor memory cell

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Clinton Corners, NY, United States of America

Haluk O Askin