Everspin Technologies, Inc.

Motorola Corporation

Freescale Semiconductor,inc.

Halbert S Lin

Thomas Andre

Syed M Alam

Chitra K Subramanian

Matthew Ronald Croft

Joseph J Nahas

Dietmar Gogl

Bradley J Garni

Brad John Garni

In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Memory system with timing overlap mode for activate and precharge operations

A boosted supply voltage generator is selectively activated and deactivated to allow operations that are sensitive to variations on the boosted voltage to be performed with a stable boosted voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner. Such techniques include storing state information corresponding to the voltage generator when deactivated, where the stored state information is used when reactivating the voltage generator. Stored state information can include a state of a clock signal provided to the voltage generator.

Boosted supply voltage generator and method therefore

A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations, generating a mock current to emulate current expected during normal operation, and erasing data stored on the memory device.

Tamper detection and response in a memory device

Memory device with timing overlap mode and precharge timing circuit

A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits using an additional offset current, and compare the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time.

Method of writing to a spin torque magnetic random access memory

A spin-torque magnetoresistive memory includes array read circuits and array write circuits coupled to an array of magnetic bits. The array read circuits sample magnetic bits in the array, apply a write current pulse to the magnetic bits to set them to a first logic state, resample the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. For each of the magnetic bits in the page having the second logic state, the array write circuits initiate a write-back, wherein the write-back includes applying a second write current pulse having opposite polarity in comparison with the first write current pulse to set the magnetic bit to the second state. A read or write operation may be received after initiation of the write-back where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time. An offset current may also be used during resampling.

Boosted supply voltage generator for a memory device and method therefore

A word line supply voltage generator is selectively activated and deactivated to allow internal memory operations that are sensitive to variations on word line voltages to be performed with a stable word line voltage. Techniques for deactivating and reactivating the voltage generator are also disclosed that enable more rapid recovery from deactivation such that subsequent operations can be commenced sooner.

Word line supply voltage generator for a memory device and method therefore

A method includes sampling magnetic bits, applying a write current pulse to the magnetic bits to set them to a first logic state, resampling the magnetic bits, and comparing the results of sampling and resampling to determine the bit state for each magnetic bit. A read or write operation may be received after initiation of writing back magnetic bits having the second state, where the write-back can be aborted for a portion of the bits in the case of a write operation. The write-back may be performed such that different portions of the magnetic bits are written back at different times, thereby staggering the write-back current pulses in time. An offset current may also be used during resampling.

Memory device with timing overlap mode

A word line driver circuit allows for dynamic selection of different word line voltages for selection and deselection of memory cells included in a resistive memory array in a manner that reduces circuit complexity, device count, and leakage currents.

Word line driver circuit

A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations and generating a mock current to emulate current expected during normal operation.

A method includes destructively reading bits of a spin torque magnetic random access memory and immediately writing back the original or inverted values. A detection of the majority state of the write back bits and a conditional inversion of write back bits are employed to reduce the number of write back pulses. A subsequent write command received within a specified time or before an original write operation is commenced will cause a portion of the write back pulses or the original write operation pulses to abort. Write pulses during subsequent write operations will follow the conditional inversion determined for the write back bits during destructive read.

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Austin, TX, United States of America

Halbert S Lin