Samsung Electronics Co., Ltd.

Haksoo Yu

Hyojin Choi

Chulwoo Park

Uksong Kang

Dae-hyun Kim

Jaeyoun Youn

Sung Hyun Lee

Jun Hee Yoo

Sua Kim

Dongsoo Kang

Joosun Choi

A bad page management system is provided to guarantee a yield of a volatile semiconductor memory device such as a DRAM. A bad page list exists in a DRAM. A page remapper in a memory controller performs a page remapping operation in parallel with a normal operation of a scheduling unit to perform a latency overhead hidden function. A chip size of the DRAM is reduced or minimized. A DRAM controller performs a latency overhead hidden function to control a DRAM.

DRAM controller having DRAM bad page management function and bad page management method thereof

A semiconductor memory cell array is provided which includes a first memory cell array area including first group memory cells arranged in a chip in a matrix of rows and columns and having a first operating speed; and a second memory cell array area including second group memory cells arranged in the chip in a matrix of rows and columns and having a second operating speed different from the first operating speed. The first and second memory cell array areas are accessed by addressing of a DRAM controller.

Semiconductor memory cell array having fast array area and semiconductor memory including the same

A semiconductor memory device performs a modified read operation or a modified write operation. The semiconductor memory device includes a memory cell array, a read circuit, and a write circuit. The semiconductor memory device further includes an operation unit performing an operation on read data obtained by the read circuit according to operation assignment information applied through an address line to reduce memory access time when entering a modified read mode. In addition, the semiconductor memory device may optionally manage a normal read mode and the modified read mode and allow operation result data output from the operation unit to be written by the write circuit in the modified read mode.

Semiconductor memory device with operation functions to be used during a modified read or write mode

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Seongman-si, South Korea

Haksoo Yu