Samsung Electronics Co., Ltd.

Hakchul Jung

Jaewoo Seo

Ingyum Kim

Giyoung Yang

Sanghoon Baek

Jisu Yu

Hyeongyu You

Seungman Lim

Garoom Kim

Jiyun Han

A semiconductor device includes a substrate including a first device region and a second device region, a first active pattern on the first device region, a second active pattern, which has a width smaller than the first active pattern, on the second device region, a first channel pattern on the first active pattern, a first source/drain pattern connected to the first channel pattern, a second channel pattern on the second active pattern, a second source/drain pattern connected to the second channel pattern, and a gate electrode that extends from the first channel pattern to the second channel pattern in a first direction. The first channel pattern includes a plurality of semiconductor patterns, which are vertically stacked and spaced apart from each other. The second channel pattern protrudes vertically from the second active pattern.

Semiconductor device and method of fabricating the same

An integrated circuit includes a standard cell including a first active region extending in a first direction and having a first width, and a filler cell including a second active region of a same type as that of the first active region and being adjacent to the standard cell in the first direction, the second active region extending in the first direction and having a second width which is greater than the first width, wherein the standard cell further includes a first tapering portion of the same type as that of the first active region, the first tapering portion being arranged between the first active region and the second active region.

Integrated circuit including standard cell and filler cell

An integrated circuit includes a plurality of logic cells arranged in a first row extending in a first direction and including different types of active areas extending in the first direction, a filler cell arranged in a second row adjacent to the first row in a second direction orthogonal to the first direction and extending in the first direction, and a first routing wiring line arranged in the second row and connecting a first logic cell and a second logic cell apart from each other by a first distance among the plurality of logic cells. A height of the first row is different from a height of the second row.

Integrated circuit and method of designing the same

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Seoul, South Korea

Hakchul Jung