Cadence Design Systems, Inc.

Canesta, Inc.

Microsoft Technology Licensing, LLC

Hakan Yalcin

Cyrus Soli Bamji

Mohammad S Mortazavi

Pawan Kulshreshtha

Karem A Sakallah

Robert J Palermo

Robert J Palmero

Xinqiao Liu

Krishna Prasad Belkhale

Ender Tunc Eroglu

Vibhor Garg

A system and method are provided for common path pessimism removal or reduction (CPPR) in a timing database provided to guide transformative physical optimization/correction of a circuit design for an IC product to remedy operational timing violations detected in the circuit design. Pessimism is reduced through generation of a common path pessimism removal (CPPR) tree structure of branching nodes, and operational timing characteristics of each node. The CPPR tree structure is used to avoid exponential phases propagating in an exploratory manner through the system design, as well as the resultant memory footprint thereof. Additionally, back-tracing node-by-node through the circuit design for each and every launch and capture flip flop pair end point through each possible path thereof is avoided.

System and method for common path pessimism reduction in timing analysis to guide remedial transformations of a circuit design

TOF and color sensing detector structures have x-axis spaced-apart y-axis extending finger-shaped gate structures with adjacent source collection regions. X-dimension structures are smaller than y-dimension structure and govern performance, characterized by high x-axis electric fields and rapid charge movement, contrasted with lower y-axis electric fields and slower charge movement. Preferably a potential barrier is implanted between adjacent gates and a bias gate is formed intermediate a gate and associated source region. For color detection sensor devices, gate bias voltage signals V, Vcoupled to the finger-shaped gate structures are high during sub-integration periods tand are low during a shorter charge movement period t. In one embodiment, alternate finger-shaped gate structures preferable have different high magnitude sub-integration period voltages that enable detected ambient optical energy of different wavelengths to be discerned. Resultant detector structures can be operated at the more extreme gate voltages that are desirable for high performance.

Methods and devices for improved charge management for three-dimensional and color sensing

Rapid calibration of a TOF system uses a stationary target object and electrically introduces phase shift into the TOF system to emulate target object relocation. Relatively few parameters suffice to model a parameterized mathematical representation of the transfer function between measured phase and Z distance. The phase-vs-distance model is directly evaluated during actual run-time operation of the TOF system. Preferably modeling includes two components: electrical modeling of phase-vs-distance characteristics that depend upon electrical rather than geometric characteristics of the sensing system, and elliptical modeling that phase-vs-distance characteristics that depending upon geometric rather than electrical characteristics of the sensing system.

Method and system for fast calibration of three-dimensional (3D) sensors

A high accuracy method for transistor-level static timing analysis is disclosed. Accurate static timing verification requires that individual gate and interconnect delays be accurately calculated. At the sub-micron level, calculating gate and interconnect delays using delay models can result in reduced accuracy. Instead, the proposed method calculates delays through numerical integration using an embedded circuit simulator. It takes into account short circuit current and carefully chooses the set of conditions that results in a tight upper bound of the worst case delay for each gate. Similar repeating transistor configurations of gates in the circuit are automatically identified and a novel interpolation based caching scheme quickly computes gate delays from the delays of similar gates. A tight object code level integration with a commercial high speed transistor-level circuit simulator allows efficient invocation of the simulation.

Transistor-level timing analysis using embedded simulation

TOF and color sensing detector structures have x-axis spaced-apart y-axis extending finger-shaped gate structures with adjacent source collection regions. X-dimension structures are smaller than y-dimension structure and govern performance, characterized by high x-axis electric fields and rapid charge movement, contrasted with lower y-axis electric fields and slower charge movement. Preferably a potential barrier is implanted between adjacent gates and a bias gate is formed intermediate a gate and associated source region. Resultant detector structures can be operated at the more extreme gate voltages that are desirable for high performance.

A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit's control inputs and their useful combinations is used to improve accuracy. The control inputs and data inputs for a circuit block are identified. Each functionally meaningful or useful control input combination is applied to the circuit block, and the topological delay for the data inputs are determined only along the paths that are not blocked by the control inputs. The delays along paths that are blocked are ignored. The analysis is further augmented by determining the topological delay for all paths originating at control inputs, without regard to blocking of paths, so as to reduce the chance for possible underestimation of delays from the data inputs. A final timing model may include the combination of maximum delays along data paths for each combination of control inputs, and maximum delays along paths originating from each of the control inputs. The delay analysis may account for different input slews and load capacitances, and the results may be expressed in tabular or matrix form. A useful technique for condensing time delay information (whether scalar or tabular in form) is also provided, to simplify timing characterization of a virtual component block or circuit model. Delay tables or matrixes that are 'close' (i.e., within a specified tolerance) may be combined into a single table or matrix.

Functional timing analysis for characterization of virtual component blocks

Effective differential dynamic range in a differential pixel detector is increased by avoiding saturation effects due to common mode contribution in optical energy to be detected. Photocurrent generated by each photodetector pair is directly integrated by an associated capacitor over an integration time T. Within time T, before either integrated capacitor voltage reaches Vfor the photodetector, at least one of the capacitors is reset to a voltage such that the desired differential detector signal is still determinable. Reset may be generated externally or internally to the differential pixel detector.

Method and system to differentially enhance sensor dynamic range

A method and mechanism for performing a timing analysis on virtual component blocks, which is an abstraction of a circuit block is provided. A set of modes for a circuit block are identified, where a mode is a set of meaningful control input values. Each functionally meaningful or useful control input combination is applied to the circuit block. For each control input combination applied, a delay for each data input/output path and each control input/output path not passing through a blocked circuit node for the applied combination of control inputs is calculated. The delay information for the data paths and control paths is stored within a timing model. The delay information may include a maximum or minimum delay for the circuit block. The timing of sequential circuit blocks may also characterized using the methods and mechanisms herein.

Method and mechanism for performing improved timing analysis on virtual component blocks

A system and method for performing a timing analysis on virtual component blocks or other circuit models is provided wherein functional information obtained from the circuit's control inputs and their useful combinations is used to improve accuracy. The control inputs and data inputs for a circuit block are identified. Each functionally meaningful or useful control input combination is applied to the circuit block, and the topological delay for the data inputs are determined only along the paths that are not blocked by the control inputs. The delays along paths that are blocked are ignored. The analysis is further augmented by determining the topological delay for all paths originating at control inputs, without regard to blocking of paths, so as to reduce the chance for possible underestimation of delays from the data inputs. A final timing model may include the combination of maximum delays along data paths for each combination of control inputs, and maximum delays along paths originating from each of the control inputs. The delay analysis may account for different input slews and load capacitances, and the results may be expressed in tabular or matrix form. A useful technique for condensing time delay information (whether scalar or tabular in form) is also provided, to simplify timing characterization of a virtual component block or circuit model. Delay tables or matrixes that are &ldquo;close&rdquo; (i.e., within a specified tolerance) may be combined into a single table or matrix.

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Fremont, CA, United States of America

Hakan Yalcin