Arm Limited

Stmicroelectronics International N.v.

Hakan Persson

Jason Parker

Marc Zyngier

Matt Evans

Roko Grubisic

Andreas Due Engh-Halstvedt

Sean Tristram Ellis

David R Shreiner

Oskar Lars Flordal

Vinod Pisharath Hari Pai

Jesus Javier De Los Reyes Darias

Neil Andrew Jameson

Wade Walker

Christophe Viroulaud

An apparatus has a cache configured to store entries which correspond to blocks of addresses having one of a plurality of sizes as selected by a control device. When the control device has not yet indicated which size to use, cache access circuitry assumes a default size which is greater than at least one of the plurality of sizes.

Apparatus having main TLB and local TLBS, and configured to set selected size for new entry allocated to local TLB to a default size

A data processing system comprising an accelerator that acts as a common shared resource for plural applications executing in respective virtual machines. The data processing system includes an interface mapping unit that facilitates the submission of tasks from applications to the accelerator. The interface mapping unit includes physical registers that act as physical register input/output interfaces for the accelerator. The interface mapping unit exposes a plurality of virtual accelerator input/output interfaces to the applications that are then dynamically mapped to the physical register input/output interfaces by the interface mapping unit to allow applications to access, and thereby submit a task to, a given physical register input/output interface.

Data processing system for dispatching tasks from a plurality of applications to a shared resource provided by an accelerator

A data processing apparatus has multiple caches and a controller for controlling the caches. The controller and caches communicate over a first network and a second network. The first network is used for unicast communication from the controller to a specific one of the caches. The second network is used for communication of a multicast communication from the controller to two or more of the caches.

Data processing apparatus, controller, cache and method

A data processing system includes one or more processors that each execute one or more operating systems. Each operating system includes one or more applications. An accelerator provides a shared resource for a plurality of the applications and has one or more input/output interfaces for the submission of tasks to the accelerator from an application. A hypervisor manages the allocation of the input/output interfaces to the one or more operating systems and a hypervisor interface enables communication between the hypervisor and the accelerator. The system is capable of being configured such that an operating system that has been allocated an input/output interface is capable of communicating with the accelerator via the input/output interface independently of the hypervisor. A memory management unit is capable of providing an isolated region of a memory for use by the operating system while the operating system retains its allocated input/output interface.

Data processing system and method having an operating system that communicates with an accelerator independently of a hypervisor

A data processing system comprises one or more processors that each execute one or more operating systems. Each operating system includes one or more applications. The system also comprises an accelerator that provides a shared resource for a plurality of the applications, an input/output module comprising one or more input/output interfaces for the submission of tasks to the accelerator, a hypervisor that manages the allocation of the input/output interfaces to the one or more operating systems and a storage area accessible by the hypervisor and the accelerator. The accelerator is capable of writing one or more selected pieces of information representative of one or more scheduling statistics of the accelerator periodically to the storage area without having received a request for the one or more selected pieces of information from the hypervisor.

Methods of and data processing systems for handling an accelerator's scheduling statistics

A data processing system includes a host processor and a graphics processing unit operable to process data under the control of an operating system executing on the host processor. The graphics processing unit can be switched between a normal mode of operation in which the it has read and write access to data that is stored in non-protected memory regionsbut no or write-only access to any protected memory regions, and a protected mode of operation in which it has read and write access to data that is stored in protected memory regionsbut only has read-only access to any non-protected memory regions. The data processing system further comprises a mechanism for switching the graphics processing unit from its normal mode of operation to the protected mode of operation, and from its protected mode of operation to the normal mode of operation.

Data processing systems

An apparatus for processing primitives in a tile-based graphics processing system includes processing circuitry which is configured to determine, for a group of plural primitives, the rendering tiles that the group of primitives should be processed for. The processing circuitry is also configured to store, for the group of primitives, a data entry containing an indication of the identity of the plurality of primitives in the group of primitives, and an indication of the rendering tiles that it has been determined the group of primitives should be processed for.

Methods and apparatus for processing computer graphics primitives in tile-based graphics rendering system

A processing system comprises plural processing cores and a task allocator for allocating tasks to the processing cores. The processing cores perform the tasks that are allocated to them so as to produce results for the tasks, the results being stored by the processing cores in a buffer. The task allocator indicates to the processing cores memory portions within the buffer in which to store the results. When the processing cores determine that a given memory portion is becoming full, the processing cores request that the task allocator indicates a new memory portion in which to store its results. The processing system allows the task allocator to dynamically and efficiently allocate memory portions to plural processing cores without the task allocatorneeding to know the sizes of the results being produced by the processing cores.

Memory allocation in a multi-core processing system based on a threshold amount of memory

A power consumption management system for a central processing unit may include a power consumption estimation block and an activity control block. The power consumption estimation block may be configured to estimate power consumption of the central processing unit based on information related to a status of the central processing unit. The activity control block may be configured to use the estimated power consumption to determine a control to be applied to the central processing unit for regulating a rate of change in power consumption of the central processing unit.

Multi-core processor system avoiding stopping of cores too close in time

A data processing system includes one or more processors that each execute one or more operating systems that include one or more applications; an accelerator that provides a shared resource for a plurality of the applications; a storage area accessible by the processors and the accelerator; and one or more input/output interfaces for control of, or the submission of tasks to, the accelerator. To initialize one of the input/output interfaces, one of the one or more processors is capable of sending a first signal to the accelerator; the accelerator is capable of writing one or more selected pieces of information representative of one or more capabilities of the accelerator to the storage area and sending a second signal to the processor; the processor is capable of reading the one or more selected pieces of information from the storage area; and the accelerator is capable of configuring the input/output interface.

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Bjarred, Sweden

Hakan Persson