Arm Limited

Hakan Lars-Goran Persson

Mark Underwood

Arne Aas

Jussi Tuomas Pennala

Andrew Christopher Rose

Jason Parker

Matthew Lucien Evans

Jakob Axel Fries

Sandeep Kakarlapudi

Ian Victor Devereux

Gareth Rhys Stockwell

Sven Ola Johannes Hugosson

Jian Wang

Vinod Pisharath Hari Pai

Robert John Rees

Steven John Price

Jesus Javier De Los Reyes Darias

Vahan Ter-Grigoryan

Muhammad Ali Shami

When encoding a block of data elements in an array of data elements, the data values for data elements in the block are represented and stored in a data packet as truncated data values using a subset of one or more most significant bits of the respective bit sequences for the data values of the data elements. A rounding mode is selected from a plurality of available rounding modes that can be applied when decoding the block of data elements and an indication of the selected rounding mode is provided along with the encoded data packet. The rounding mode is associated with one or more rounding bit sequence(s) that can then be applied to the truncated data values when decoding the data packet to obtain decoded data values for the data elements in the block.

Encoding data arrays

When operating a data processing system comprising a data encoder operable to perform a first encoding scheme that is configured for processing sets of data arranged in a first data format, for a plurality of sets of data received in a second, different data format, the bits for at least some of the received plurality of sets of data in the second data format are re-ordered to map the bits for the at least some of the received plurality of sets of data in the second data format into the first arrangement of bits associated with the first data format to thereby generate from the received plurality of sets of data in the second data format one or more sets of data in the first data format for processing using the first encoding scheme.

When a processing resource of a data processing system is to perform processing tasks for applications executing on a host processor, the host processor prepares a plurality of command streams to cause the processing resource to perform the processing tasks. When a processing task to be added to a command stream has a dependency on a processing task or tasks that will be included in another command stream, a wait command is added to the command stream that is to include the processing task that has a dependency on a processing task or tasks that will be included in the another command stream, to cause the processing resource to delay executing subsequent commands in the command stream after the wait command, until the processing resource has reached a particular position in the another command stream.

Preparing and executing command streams in data processing systems

When executing a program on a data processor comprising an execution unit for executing instructions in a program to be executed by the data processor, the execution unit being associated with one or more hardware units operable to execute instructions, at least one instruction in a program is associated with an indication of whether the instruction should be issued directly for execution by a hardware unit or should be intercepted during its execution by the execution unit. The execution unit then, when decoding the instruction for execution by a hardware unit in the program, determines from the indication associated with the instruction whether the instruction should be issued directly for execution by a hardware unit or intercepted during its execution by the execution unit, and issues the instruction for execution by a hardware unit directly, or pauses execution of the instruction and performs another operation, accordingly.

Control of instruction execution in a data processor

A data processing system in which a host processor prepares command streams for causing an accelerator of the data processing system to perform processing tasks for an application executing on the host processor, each command stream including a sequence of commands for implementation by the accelerator. When a request for processing includes protected content, the host processor includes within a command for a command stream, an indication that a subsequent sequence of one or more command(s) within that command stream associated with the protected content is to be implemented by the accelerator in a protected mode of operation. Then, when that command is executed, the accelerator initiates or requests a switch into the protected mode of operation.

Data processing system with protected mode of operation for processing protected content

A data processing system in which a host processor prepares command streams for causing an accelerator of the data processing system to perform processing tasks for an application executing on the host processor, each command stream including a sequence of commands for implementation by a command stream execution unit of the accelerator. A pre-execution unit is provided that is operable to interpret commands fetched from command stream storage before the command is provided to the command stream execution unit for implementation to determine whether the pre-execution unit is able to perform an action in response to the command and, when the pre-execution unit is able to do so, to perform an action in response to the command.

Data processing systems

A data processing system comprises one or more data processing units, a configurable interconnect and control circuitry. The control circuitry allocates one or more of the data processing units to a virtual machine and configures the configurable interconnect so as route one or more data processing tasks from the virtual machine to the one or more data processing units allocated for use by that virtual machine. This can provide a flexible and adaptable data processing system for carrying out the data processing tasks of a virtual machine, with the particular allocation of data processing units being substantially transparent to the virtual machine.

A graphics processing system comprises a pair of graphics processing units that are connected to each other via communications bridges that can allow communication between the connected graphics processing units. One of the graphics processing units is operable to act as a master graphics processing unit controlling graphics processing operations on the other graphics processing unit which is operable as a slave graphics processing unit to perform graphics processing operations under the control of the master graphics processing unit. Each graphics processing unit of the pair of graphics processing units is also capable of operating in a standalone mode, in which the graphics processing unit operates independently of the other graphics processing unit to perform a graphics processing task.

Multiple GPU graphics processing system

A multiple stage memory management unit (MMU) comprises a first MMU stage configured to translate an input virtual memory address to a corresponding intermediate memory address, the first MMU stage generating a set of two or more intermediate memory addresses including the corresponding intermediate memory address; and a second MMU stage configured to translate an intermediate memory address provided by the first MMU stage to a physical memory address, the second MMU stage providing, in response to an intermediate memory address received from the first MMU stage, a set of two or more physical memory addresses including the physical memory address corresponding to the intermediate memory address received from the first MMU stage; the first MMU stage being configured to provide to the second MMU stage for translation, intermediate memory addresses in the set other than any intermediate memory addresses in the set for which the second MMU stage will provide a physical memory address as a response to translation of one of the other intermediate memory addresses in the set.

Multiple stage memory management

A data processing apparatus and a method of processing data are disclosed, in which address translations between first addresses used in a first addressing system and second addresses used in a second addressing system are locally stored. Each stored address translation is stored with a corresponding identifier. In response to an invalidation command to perform an invalidation process on a selected stored address translation the selected stored address translation is invalidated, wherein the selected stored address translation is identified in the invalidation command by a specified first address and a specified identifier. The invalidation process is further configured by identifier grouping information which associates more than one identifier together as a group of identifiers, and the invalidation process is applied to all stored address translations which match the specified first address and which match any identifier in the group of identifiers to which the specified identifier belongs.

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Bjarred, Sweden

Hakan Lars-Goran Persson