Stmicroelectronics Gmbh

Cypress Semiconductor Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Hakan C Ozdemir

Razmik Karabed

Richard David Barndt

Fereidoon Heydari

Vincent Brendan Ashe

Jason D Byrne

Francesco Rezzi

Kuhong Jeong

Shaohua Yang

Jonathan James Ashley

Victor A Krachkovsky

Zhiwei Wu

Francesco Brianti

Ebad Ahmed

Sadik O Arf

A data encoder includes an encoding logic circuit configured to encode input data to apply run length limiting using state splitting of a code trellis, and a lookup table configured to apply a block-enumerable map on an un-split version of the code trellis, wherein entries in the lookup table are compressed.

State-split based encoder and decoder with table compression

A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses 'soft' data indicative of how reliable bits of data are when read out. Such a method may use an update module for receiving and manipulating the soft-decision data and iteratively change bits or groups of bits based upon an ordering of the reliability factors. Then a calculator module may determine the total number of errors still remaining after each iteration. Determining just the total number of errors instead of the actual locations is far less computationally intensive, and therefore, many combination of potential flip-bit combination may be analyzed quickly to determine if any combination might reduce the total number of errors enough to be handled by the conventional hard-decision ECC decoding method.

Non-polynomial processing unit for soft-decision error correction coding

An embodiment of a read channel includes a filter, an interpolator, a recovery circuit, an error detector, a reverse interpolator, and a filter calibrator. The filter is operable to receive a raw sample of a signal and a coefficient-correction value, generate a filtered sample from the raw sample and a pre-established coefficient, and change the coefficient in response to the coefficient-correction value. The interpolator is operable to interpolate the filtered sample, and the recovery circuit is operable to generate a data symbol from the interpolated sample. The error detector is operable to generate an ideal sample from the data symbol and to generate a difference between the ideal sample and the interpolated sample, and the reverse interpolator is operable to reverse interpolate the difference. The filter calibrator is operable to receive the raw sample and to generate the coefficient-correction value from the raw sample and the reverse-interpolated difference.

Read channel operable to calibrate a coefficient of a filter, such as an FIR filter, disposed before an interpolated-timing-recovery circuit, and related integrated circuit, system, and method

A system and method for encoding a stream of bits with a run-length limited high-rate reverse order encoding schema. According to one embodiment, an RLL encoding block includes a receiver having a precoder operable to receive a stream of N-bits having symbols of M-bits in length, a histogram operable to identify an index symbol of M-bits that does not occur within the received stream of N-bits. It is this index symbol that may be used as the key to encoding a block of symbols so as to ensure unique decodability when RLL decoding. Finally, an encoder operable to perform an exclusive-or operation on each symbol with the next symbol stored in the stream. Such an encoding system only adds one symbol of M bits in length to a block of N bits and still results in a stream of bits sufficient to support high-rate requirements and strict timing loop control.

High-rate reverse-order run-length-limited code

A system and method for correcting errors in an ECC block using erasure-identification data when generating an error-locator polynomial. In an embodiment, a ECC decoding method, uses 'erasure' data indicative of bits of data that are unable to be deciphered by a decoder. Such a method may use an Berlekamp-Massey algorithm that receives two polynomials as inputs; a first polynomial indicative of erasure location in the stream of bits and a syndrome polynomial indicative of all bits as initially determined. The Berlekamp-Massey algorithm may use the erasure identification information to more easily decipher the overall codeword when faced with a error-filled codeword.

Error-locator-polynomial generation with erasure support

A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses 'soft' data indicative of how reliable bits of data are when read out. Such reliability information may be used to identify particular symbols with a higher likelihood of error such that these symbols may be changed in an attempt to reduce the total number of errors in the data. In an embodiment, a soft-decision ECC decoding path may include a reliability checker operable to receive bits of data read from a data store and operable to associate a reliability factor with each bit of data. Then, an update module may iteratively change bits or groups of bits based upon an ordering of the reliability factors.

Low-complexity soft-decision decoding of error-correction codes

A method and apparatus for reducing noise in a communication signal is provided. The method includes converting raw channel data from the communication signal to a sequence of transition code symbols, each symbol having a plurality of bits, each bit having a position within the symbol. The method also includes sending the bits of each symbol to a plurality of bins, each bin corresponding to the position of each bit within the symbol. For each bin having a number of transitions greater than a number of non-transitions, the method also includes flipping every bit in the bin and setting a corresponding bit in a flip control word to a first value. The method still further includes binary adding the flip control word to each transition code symbol.

High-rate transition control code for magnetic recording channels

A detector recovers servo data from a servo signal generated by a read-write head, and determines the head-connection polarity from the recovered servo data. Such a detector allows a servo circuit to compensate for a reversed-connected read-write head, and thus allows a manufacturer to forego time-consuming and costly testing to determine whether the head is correctly connected to the servo circuit.

Circuit and method for detecting the phase of a servo signal

A data-storage disk includes a disk sector for storing data and a servo wedge located at the beginning of the sector. The servo wedge indentifies the sector in conjunction with both an initial positioning of a read-write head and a data read or write operation. By using a servo wedge to provide both an initial head position on disk spin up and a head position during a read or write operation, one can increase a disk's data-storage capacity by reducing the number of, or altogether eliminating, spin-up wedges.

Data-storage disk having few or no spin-up wedges and method for writing servo wedges onto the disk

A phase-acquisition (PA) loop for a read channel comprises an accumulator, a comparator, and a filter. The accumulator holds an acquired phase-correction value corresponding to a difference between a phase of a sample clock and a phase of data carried by a read signal, and provides the acquired phase-correction value to a circuit that modifies the read signal to compensate for the phase difference. The comparator receives a reference phase-correction value that also corresponds to the difference between the phases of the sample clock and the data, and generates an error signal that is related to a difference between the reference and acquired phase-correction values. And the filter causes the acquired phase-correction value to have a predetermined relationship to the reference phase-correction value. Because such a PA loop may require significantly fewer samples of a read-signal preamble than prior PA loops requires to acquire the phase between a sample clock and data carried by a read signal, such a PA loop may allow one to significantly reduce the length of the preamble.

Phase acquisition loop for a read channel and related read channel, system, and method

A gain controller for a gain loop of a read channel includes a comparator circuit, an accumulator circuit, and a function circuit. The comparator circuit determines an error between an actual sample of a read signal and a corresponding ideal sample of the read signal, and the accumulator circuit holds a gain-correction value and adjusts the gain-correction value in response to the error. The function circuit generates a gain-correction signal by performing a predetermined mathematical operation involving the gain-correction value, and provides the gain-correction signal to a variable-gain amplifier that is operable to amplify actual samples of the read signal. Because such a gain controller allows one to locate the variable-gain amplifier (VGA) after the analog-to-digital converter (ADC) in a read channel, the gain controller may significantly reduce the latency of the gain-acquisition (GA) loop or the gain-tracking (GT) loop of the read channel. The gain controller may also allow the GA loop and the GT loop to be completely contained with in the digital portion of the read channel.

Gain controller for a gain loop of a read channel and related gain loops, read channels, systems, and methods

A new technique for Hard Disk Drive (HDD) servo-burst demodulation is provided. A 4-samples per dibit Discrete Fourier Transform (DFT) amplitude estimation is used to calculate the read-head servo-position error signal. Comparatively, the conventional method of burst demodulation&#x2014;called burst integration&#x2014;typically uses more than 8 samples/dibit. Consequently, the new 4-samples/dibit DFT burst-demodulation scheme requires fewer samples per dibit than does burst integration, thus reducing the disk space occupied by the burst data while increasing the performance as compared to burst integration. Furthermore, the DFT scheme does not require the samples to be synchronized to any particular points of the servo burst, and can include an averaging algorithm that further improves performance for a given Signal to Noise Ratio (SNR). Moreover, the same sample-clocking circuit that detects the Gray Code servo information can also implement the DFT burst-demodulation scheme to demodulate the servo burst.

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San Jose, CA, United States of America

Hakan C Ozdemir