Motorola Corporation

Semiconductor Components Industries, LLC

Hak-Yam Tsoi

Edouard D De Fresart

Pak M Tam

Henry G Hughes

Jeffrey Pearse

Frank A Shemansky, Jr

Paul L Bergstrom

Edouard De Fr&eacute;sart

Irenee M Pages

Rainer Thoma

Quang X Nguyen

DaXue Xu

Cynthia Trigas

A semiconductor wafer level package used to encapsulate a device fabricated on a semiconductor substrate wafer before dicing of the wafer into individual chips. A cap wafer may be bonded to the semiconductor substrate using a low temperature frit glass layer as a bonding agent. The frit glass layer is in direct contact with the device. A hermetic seal is formed by a combination of the semiconductor substrate wafer, the cap wafer and the frit glass layer. A second embodiment of the package does not contain a cap wafer.

Method of manufacturing a semiconductor wafer level package

A vertically diffused FET ( ) is fabricated on a semiconductor die ( ) that includes an N substrate ( ) and an N epitaxial layer ( ). The FET ( ) has a source region ( ) and a channel region ( ) near a front surface ( ) of the epitaxial layer ( ), and a drain region in the substrate ( ). A trench ( ) extends through the epitaxial layer ( ) to the substrate ( ). A conductive layer ( ) fills the trench ( ), thereby forming a conductive plug ( ) electrically coupled to the substrate ( ). The conductive plug ( ) forms a top side drain electrode of the FET ( ).

Semiconductor device and method for fabricating the same

A power MOSFET device (40) includes one or more localized regions of doping (61,62,63) formed in a more lightly doped semiconductor layer (42). The one or more localized regions of doping (61,62,63) reduce inherent resistances between the source regions (47,48) and the drain region (41) of the device. The one or more localized regions of doping (61,62,63) are spaced apart from the body regions (44,46) to avoid detrimentally impacting device breakdown voltage. In an alternative embodiment, a groove (122) or trench (152) design is incorporated to reduce JFET resistance (34). In a further embodiment, a gate dielectric layer having a thick portion (77,97,128,158) and thin portions (76,126,156) is incorporated to enhance switching characteristics and/or breakdown voltage.

Power MOSFET device having low on-resistance and method

A bipolar transistor (10) includes a collector region (13), a base region (14) in the collector region (13), and an emitter region (20) in the base region (14). A portion (18) of an electrical conductor (16) is located over a base width (23) of the bipolar transistor (10). The emitter region (20) is self-aligned to the portion (18) of the electrical conductor (16) and is preferably diffused into the base region (14) in order to decrease the base width (23) without relying on extremely precise alignment between base region (14) and the portion (18) of the electrical conductor (16). The portion (18) of the electrical conductor (16) is used to deplete a portion of the base width (23) of the bipolar transistor (10).

Method for making bipolar transistor

A method for forming a semiconductor device includes forming insulated gate regions (122,222) on a substrate (26) using a first photo-masking step, forming a base region (47) through an opening (143) between the insulated gate regions (122,222), and forming a source region (152) within the base region (47). Next, a protective layer (61) is formed and selectively patterned using a second photo-masking step to form an opening (62) within the first opening (143) and an opening (63) above one of the insulated gate regions (122). Next, a portion (66) of the substrate (26) and a portion (67) of the insulated gate region (122) are removed. Ohmic contacts (74,76) are then formed and patterned using a third photo-masking step. Additionally, a termination structure (81) is described.

Method of manufacturing a semiconductor device and termination structure

A DMOS device with field oxide formed in the channel between adjacent transistors and an impurity implanted through the same opening in which the field oxide is formed. The gate is deposited over the field oxide and spaced from the supporting epitaxial layer by the field oxide to reduce the gate-to-drain capacitance. The implanted impurity below the field oxide reduces ON resistance of the device.

Growing community of inventors

Scottsdale, AZ, United States of America

Hak-Yam Tsoi