Samsung Electronics Co., Ltd.

Hak-seung Lee

Kwang-Jin Moon

Tae-Seong Kim

Dong-Chan Lim

Dae-suk Lee

Dae-Suk Lee

A semiconductor package includes a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip. The first semiconductor chip includes a substrate having a first via hole, an insulation interlayer formed on the substrate and having a first bonding pad in an outer surface thereof and a second via hole connected to the first via hole and exposing the first bonding pad, and a plug structure formed within the first and second via holes to be connected to the first bonding pad. The second semiconductor chip includes a second bonding pad bonded to the plug structure which is exposed from a surface of the substrate of the first semiconductor chip.

Semiconductor device, semiconductor package and method of manufacturing the same

Semiconductor chips and methods of manufacturing the same are provided. The semiconductor chip includes a substrate, an interlayer insulation layer including a bottom interlayer insulation layer on an upper surface of the substrate and a top interlayer insulation layer on the bottom interlayer insulation layer, an etch stop layer between the bottom interlayer insulation layer and the top interlayer insulation layer, a landing pad on the interlayer insulation layer, and a through via connected to the landing pad through the substrate, the interlayer insulation layer, and the etch stop layer. The etch stop layer is isolated from direct contact with the landing pad.

Growing community of inventors

Seoul, South Korea

Hak-seung Lee