Samsung Electronics Co., Ltd.

Hak-Kyoon Byun

Tae-Hun Kim

Heung-Kyu Kwon

Sang-Uk Han

Sung-Yong Park

Jung-Do Lee

Taehoon Kim

Jongkook Kim

Jeong-O Ha

Youn-sung Ko

Jung-hwan Woo

Hyun-jung Song

Seonhyang You

Seon-Hyang You

Se-nyun Kim

Provided is a semiconductor package and a method for fabricating the semiconductor package. The semiconductor package may include a first package having a first semiconductor chip mounted on a first substrate and a second package having a second semiconductor chip mounted on a second substrate, the second substrate being bent to cover a side of the first package to contact the first substrate such that the first and second packages are connected electrically.

Semiconductor package and method for manufacturing the same

An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure.

Electronic device having stack-type semiconductor package and method of forming the same

A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.

Wiring substrate having variously sized ball pads, semiconductor package having the wiring substrate, and stack package using the semiconductor package

An apparatus for and a method of detaching a semiconductor chip from a tape minimize the likelihood that the semiconductor chip will crack. The apparatus includes a holder, a first ejector having an upper end, and a second ejector whose upper end is disposed centrally of that of the first ejector. The holder has an upper portion and a through-hole extending through the upper portion. The ejectors have upper ends that are extendable and retractable out of and back into the holder via the through-hole in the upper portion of the holder. A tape to which at least one semiconductor chip is attached is set against the upper portion of the holder. The first ejector is extended a first distance from the holder to push the semiconductor chip upward. The second ejector is extended from the holder by a second distance larger than the first distance so as to push the semiconductor chip further upward. Thus, the tape is progressively detached from the semiconductor chip.

Apparatus for detaching a semiconductor chip from a tape

Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.

Semiconductor device package

Growing community of inventors

Asan-si, South Korea

Hak-Kyoon Byun