Lantiq Deutschland Gmbh

Intel Corporation

Maxlinear, Inc.

Lantiq Beteiligungs Gmbh & Co. Kg

Hak Keong Sim

Raj Kumar Jain

Ingo Volkening

Chunfeng Hu

Shridhar Mubaraq Mishra

Ravindra Singh

Ritesh Banerjee

Tina Zhang

Chee Kiang Goh

Eric Mouchel La Fosse

Paul Louis Chazhoor

An on-chip data packet processing method and corresponding integrated circuit, wherein data packets are received at an ingress port and processed with an on-chip wire-speed engine. The processing comprises adding metadata to the data packets, forwarding the processed data to an on-chip QoS unit, altering the metadata of the data packets and/or providing further metadata to the data packets. The data packets are forwarded from the on-chip QoS unit to an on-chip data consumer. If the data consumer is a processing unit the data packets are processed in a first processing step, redirected from the processing unit to the QoS unit and the step of forwarding the data packets to an on-chip data consumer is repeated.

Data packet processing system on a chip

An Ethernet device comprises a plurality of Management Data Input/Output (MDIO) Manageable Device (MMD) registers storing Ethernet register field definitions that operate a management interface to one or more MMD devices. An MDIO controller, communicatively coupled to the plurality of MMD registers can control communication via the management interface to the one or more MMD devices based on a mapping of the set of Ethernet register field definitions to the plurality of MMD registers, and dynamically modify the mapping of the set of Ethernet register field definitions to the plurality of MMD registers.

Method and apparatus to re-configure MDIO registers on an ethernet device

An Ethernet switch has at least one ingress/egress port which is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaces each of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit modules which receive GE and FE packets from, and transmit GE and FE packets to, the interfaces.

Configurable fast ethernet and gigabit ethernet data port

A line card is proposed in which one or more DMT processing modulescommunicate with a data link layer platform, such as an ATM, POSPHY or Ethernet processor. The data relating to a single symbol is transmitted between the data link layer platform and a given one of DMT processing modules in a plurality of data portions spaced apart in time. The data portions relating to different channels of a given DMT processing module (or to different DMT processing modules) are interleaved in time. Since the data portions of a given symbol are spaced apart in time, the data relating to a single symbol is transmitted over a longer time period than in conventional devices which reduces the effective burstiness of the traffic, and thus reduces the memory requirements of the data link layer platform.

Traffic shaping between the DMT processor and data link layer processor of a line-card

An Ethernet switch has at least one ingress/egress portwhich is operable in two modes, in a first mode as a GE port and in a second mode as a plurality of FE ports. The port has 8 MAC interfaceseach of which is capable of receiving/transmitting FE packets, and at least one of the MAC interfaces can be configured to receive/transmit GE packets. Thus, the port has two modes of operation. The port further includes receive and transmit moduleswhich receive GE and FE packets from, and transmit GE and FE packets to, the interfaces. If there are 8 such ports in the Ethernet switch, then by switching different numbers of the ports between the two modes, the switch may operate in 9 different modes: as 8 GE ports, 7 GE ports and 8 FE ports, 2 GE ports and 48 FE ports, 1 GE port and 56 FE ports, or simply as 64 FE ports.

Systems and methods for processing data signals are described. In one implementation, a demodulator and a first decoder unit, such as a convolutional encoder or a quadrature amplitude modulation decoder, for receiving the output of the demodulator, decoding the second level of encoding and outputting a decoded signal and a first error indication signal indicative of errors in the decoded signal are provided. The decoded signal may be passed through a de-interleaving unit to form a de-interleaved signal. The first location signal may be passed to an identifier unit which receives it, and from it produces a second error indication signal indicative of the errors in the de-interleaved signal. The de-interleaved signal and the second error indication signal may be transmitted to a redundancy decoder, where the signals may be used to perform redundancy decoding.

Decoder system for data encoded with interleaving and redundancy coding

A system for processing a data signal (such as an ADSL or VDSL signal) includes a first decoder unit, such as a convolutional decoder or a QAM decoder, for receiving the data signal, decoding the second level of encoding and outputting a decoded signal and a first error indication signal indicative of errors in the decoded signal. A redundancy decoder employs the decoded signal and the first error indication signal (or transformed versions thereof) to perform redundancy decoding.

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Singapore, Singapore

Hak Keong Sim