Hitachi-High-Technologies Corporation

Ricoh Company, Ltd.

Kioxia Corporation

Kabushiki Kaisha Toshiba

Hitachi, Ltd.

Hitachi High-Tech Corporation

Hodogaya Chemical Co., Ltd.

Toshiba Memory Corporation

Hajime Yamazaki

Mitsuru Oonuma

Yoko Sato

Akihito Wakui

Akihisa Makino

Sakuichiro Adachi

Masahiko Iijima

Shinji Yonezawa

Hiroshi Mitsumaki

Tadashi Ohishi

Manabu Ando

Keiko Yoshikawa

Takahiro Miomo

Hiroshi Hamada

Tomonori Mimura

Atsushi Katayama

Hiroyuki Kuriyama

Albert Wohland

Shinji Otani

Takeshi Yogi

Alfred Resch

Hironobu Miyamoto

Hiroshi Yao

Hirokuni Yano

Mitsunori Tadokoro

Konosuke Watanabe

Hiroaki Kataoka

Haruka Mori

Prashob Ramachandran Nair

Yasunori Nakamura

Akihiro Nagatani

Makoto Domon

Taku Sakazume

Hidemi Koike

Katsuaki Takahashi

Takahiro Yagishita

Hiroyuki Yamaguchi

Shigeki Matsubara

Makoto Nagaoka

Yasuhiro Kimura

Yuya Matsuoka

Hirokazu Takeuchi

Terumi Tamura

Masaki Shiba

Koichi Kashima

Tatsuya Sumiyoshi

Kenichi Hirami

Yoshimi Niisato

Yukie Kumagai

Eriko Otsu

Takahiro Totsuka

Kenichiro Nishiki

Kiyokazu Takasou

Mitsusato Hara

Eiji Sukigara

According to one embodiment, a memory system includes a plurality of nonvolatile memory chips and a controller. The controller manages whether each of the nonvolatile memory chips is in a busy state or not. When one or more requests issued by a host are stored in at least one queue of the host, the controller identifies, from the one or more requests, a first request for a first nonvolatile memory chip that is not in the busy state. The controller executes a process in accordance with the identified first request.

Memory system and method of controlling memory chips

A memory controller of a memory system classifies input and output commands issued by a host into a group of read commands and a group of write commands, and manages the group of read commands and the group of write commands using first and second queues, respectively. The controller continuously processes a first group of commands among the group of read commands and the group of write commands until a first time period has elapsed from a start of the continuous processing of the first group of commands. In response to the first time period having elapsed, the controller switches a process target from the first group of commands to a second group of commands that is different from the first group of commands and selected among the group of read commands and the group of write commands.

Memory system

A high-throughput automatic analyzer integrates a biochemical analysis section and a blood coagulation analysis section. The analyzer is capable of achieving a reduction in size, system cost, and lifecycle cost. The automatic analyzer includes: a reaction disk; a first reagent dispensing mechanism that dispenses a reagent to reaction cells on the reaction disk; a photometer that irradiates a reaction solution in the reaction cell with light; a reaction cell cleaning mechanism; a reaction vessel supply unit that supplies a disposable reaction vessel for mixing and reacting a sample and a reagent with each other; a second reagent dispensing mechanism that dispenses a reagent to the disposable reaction vessel; a blood coagulation time measuring section that irradiates a reaction solution in the disposable reaction vessel with light to detect transmitted or scattered light; and a sample dispensing mechanism that dispenses a sample to the reaction cell and the disposable reaction vessel.

Automatic analyzer

According to one embodiment, a storage controller is configured to control a storage device capable of, upon issuance of a predetermined command, causing a storage including a temperature sensor to perform a temperature measurement to update a temperature measurement value. The storage controller includes a timer configured to notify a timeout when an elapsed time from a last issuance of the predetermined command reaches a predetermined time, and a controller configured to, when the timeout is notified, issue to the storage a command for updating the temperature measurement value.

Storage controller, storage device, and program

A memory system includes a first nonvolatile memory, a first processor, and a second processor. The first processor sets a first assignment amount. The second processor performs access to the first nonvolatile memory, calculates a consumed amount which is an amount according to an operation time of the first nonvolatile memory in the access, and transmits a notification to the first processor when the consumed amount reaches the first assignment amount.

According to one embodiment, a memory apparatus includes a memory device and a controller. The memory device includes a plurality of memory chips. The controller includes a plurality of memories. The controller determines whether or not the memory chip is allocated to any one memory when receiving an access request related to the memory chip from a host apparatus. The controller newly allocates the memory chip to the memory to which none of the memory chips is allocated when it is determined that the memory chips is not allocated, and enqueues a command corresponding to the access request received from the host apparatus to the memory to which the memory chip is newly allocated.

Memory apparatus and control method for command queue based allocation and management of FIFO memories

According to one embodiment, a controller executes a first operation. The first operation includes reading a plurality of data units from a nonvolatile memory and executing a process on the read plurality of data units. The process includes an inverse conversion of a conversion applied to the plurality of data units and first decoding using the plurality of data units that has executed the inverse conversion. The controller acquires first information from one of the plurality of data units that has executed the first operation. The controller compares the acquired first information with an expected value of the first information and re-executes the first operation when the acquired first information and the expected value are not equal to each other.

Memory system and method

A memory system includes a memory and a memory controller. The memory includes first and second parallel operation elements, each including a plurality of first and second storage regions, respectively, and first and second buffers, respectively. The memory controller performs operations on the memory based on first and second group information. The first group information defines first groups, each first group including one first storage region and one second storage region, and each second group including at least two first groups. The memory controller, in response to a host command targeting a first storage region, (i) acquires first data from the first buffer, and thereafter (ii) causes the memory to read out second data to the first buffer. The first storage region storing the first data and the second storage region storing the second data belong to different first groups and to the same second group.

Memory system configured with a synthesized logical block into which a plurality of data units forming an error correction frame are written

An automated analyzer has a reaction disk on which a plurality of reaction vessels capable of holding sample and reagent mixtures can be placed, a first cover for covering at least a portion of the area above the reaction disk, a second cover that can be opened and closed independently from the first cover, at least one sensor for monitoring the opening and closing of the first cover, and a control unit for monitoring a signal from the sensor and carrying out control such that if the first cover has not been opened and closed during the period until a new analysis operation is started, a pre-analysis cleaning operation, blank measurement operation, or both, are skipped.

Automated analyzer and control method for same

Uneven wear causes degradation of the individual parts of a syringe pump. Specifically, a seal piece composed of a soft material is easily damaged by uneven wear. To solve this problem, an automatic analysis device has a syringe pump that feeds and aspirates a liquid into and from a dispensing unit. The syringe pump has a syringe tube that stores a liquid, a plunger that moves up and down in the syringe tube, a plunger upper pressing component that contacts the plunger, a motive force transmitting part that transmits motive force to the plunger via the plunger upper pressing component, and a plunger lower pressing component that contacts the motive force transmitting part. The plunger upper pressing component and the motive force transmitting part make point contact with each other, and the motive force transmitting part and the plunger lower pressing component make point contact with each other.

Automatic analysis device with syringe pump

Memory system for controlling memory access based on access time of memory

According to one embodiment, a memory system includes a first memory including a message queue having first to naddresses (n&#x2265;2, n is natural number), a first pointer showing one of the first to naddresses, and a second pointer showing one of the first to naddresses, a monitor unit which detects whether the first and second pointers show the first address, and a processing unit which changes an address shown by the first pointer from the first address to an iaddress (n&#x2265;i&#x2265;2, i is natural number) when the first and second pointers show the first address. An address shown by the second pointer is incremented from the first address to a (j+1)address (j&#x2265;1, j is natural number) when first to jmessages are queued in the first to jaddresses.

Memory system using message monitoring and first and second namespaces

Growing community of inventors

Tokyo, Japan

Hajime Yamazaki