Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Hajime Yamamoto

Michiaki Sano

Koichi Ito

Kazuto Watanabe

Hiroshi Sasaki

Takashi Yamaha

Katsuya Kato

Ikue Yokomizo

Ryo Hiramatsu

Liang Li

Akihiro Tobioka

A method includes providing a first wafer including a respective set of first metal bonding pads and at least one first alignment diagnostic structure, providing a second wafer including a respective set of second metal bonding pads and a respective set of second alignment diagnostic structures, overlaying the first wafer and the second wafer, measuring at least one of a current, voltage or contact resistance between the first alignment diagnostic structures and the second alignment diagnostic structures to determine an overlay offset, and bonding the second wafer to the first wafer.

Electrical overlay measurement methods and structures for wafer-to-wafer bonding

A bonded assembly includes a first stack containing a first semiconductor die bonded to a second semiconductor die along a stacking direction, first external bonding pads formed within the first semiconductor die, and bonding connection wires. Each of the bonding connection wires extends over a sidewall of the first semiconductor die and protrudes into the first semiconductor die through the sidewall of the first semiconductor die to contact a respective one of the first external bonding pads.

Bonded assembly containing side bonding structures and methods of manufacturing the same

A bonded structure may be formed by measuring die areas of first semiconductor dies on a wafer at a measurement temperature, generating a two-dimensional map of local target temperatures that are estimated to thermally adjust a die area of each of the first semiconductor dies to a target die area, loading the wafer to a bonding apparatus comprising at least one temperature sensor, and iteratively bonding a plurality of second semiconductor dies to a respective one of the first semiconductor dies by sequentially adjusting a temperature of the wafer to a local target temperature of a respective first semiconductor die that is bonded to a respective one of the second semiconductor dies. An apparatus for forming such a bonded structure may include a computer, a chuck for holding the wafer, a die attachment unit, and a temperature control mechanism.

Distortion-compensated wafer bonding method and apparatus using a temperature-controlled backside thermal expansion layer

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Nagoya, Japan

Hajime Yamamoto