Sony Corporation

Sony Semiconductor Solutions Corporation

Sony Group Corporation

Hajime Yamagishi

Shota Hida

Kiyotaka Tabuchi

Yuusaku Kobayashi

Kazutaka Yamane

Minoru Ishida

Masaki Okamoto

Takashi Oinoue

Masanori Hosomi

Hiroshi Hasegawa

Takashi Kinoshita

Yoshiki Ebiko

Takashi Yokoyama

Eiji Sato

Mitsuharu Shoji

Shunsaku Tokito

Takayuki Sekihara

Makoto Hayafuchi

Shoji Ichikawa

Mitsuhara Shoji

Akira Yamazaki

Syunsuke Ishizaki

Yutaro Komuro

The present technology relates to a light receiving element, a distance measurement module, and electronic equipment which are capable of reducing leakage of incident light to adjacent pixels. A light receiving element includes a semiconductor layer in which photodiodes performing photoelectric conversion of infrared rays are formed in units of pixels, and a wiring layer in which a transfer transistor reading charge generated by the photodiodes is formed, and an inter-pixel light shielding unit that shields the infrared rays is formed at a pixel boundary portion of the wiring layer. The present technology can be applied to, for example, a distance measurement module that measures a distance to a subject, and the like.

Light receiving element, distance measurement module, and electronic equipment

An imaging device includes a first substrate including a pixel array and a first multilayer wiring layer. The first multilayer wiring layer includes a first wiring that receives electrical signals based on electric charge generated by at least one photoelectric conversion unit, and a plurality of second wirings. The imaging device includes a second substrate including a second multilayer wiring layer and a logic circuit that processes the electrical signals. The second multilayer wiring layer includes a third wiring bonded to the first wiring, and a plurality of fourth wirings. At least one of the plurality of fourth wirings being bonded to at least one of the plurality of second wirings. The second multilayer wiring layer includes at least one fifth wiring that is connected to the plurality of fourth wirings and that receives a power supply signal.

Semiconductor device

An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL).

Imaging device and electronic device

This technology relates to a solid-state imaging device and an electronic apparatus by which image quality can be enhanced. The solid-state imaging device includes a pixel region in which a plurality of pixels are arranged, a first wiring, a second wiring, and a shield layer. The second wiring is formed in a layer lower than that of the first wiring, and the shield layer is formed in a layer lower at least than that of the first wiring. This technology is applicable to a CMOS image sensor, for example.

Solid-state imaging device and electronic apparatus to enhance image quality

Effective use is achieved of a region in a proximity of a joining plane of semiconductor substrates in a semiconductor device including a stacked semiconductor substrate in which multilayer wiring layers of a plurality of semiconductor substrates are electrically connected to each other. The stacked semiconductor substrate includes plural semiconductor substrates on each of which a multilayer wiring layer is formed. In this stacked semiconductor substrate, the multilayer wiring layers are joined together and electrically connected to each other. In the proximity of a joining plane of the plurality of semiconductor substrates, a conductor is formed. This conductor is formed such that it is electrified in a direction of the joining plane.

Imaging device and electronic device configured by bonding a plurality of semiconductor substrates

The present technology relates to a solid-state imaging device that can reduce the number of steps and enhance mechanical strength, a method of manufacturing the solid-state imaging device, and an electronic apparatus. The solid-state imaging device includes a laminate including a first semiconductor substrate having a pixel region and at least one second semiconductor substrate having a logic circuit, the at least one second semiconductor substrate being bonded to the first semiconductor substrate such that the first semiconductor substrate becomes an uppermost layer, and a penetration connecting portion that penetrates from the first semiconductor substrate into the second semiconductor substrate and connects a first wiring layer formed in the first semiconductor substrate to a second wiring layer formed in the second semiconductor substrate. The first wiring layer is formed with Al or Cu. The present technology is applicable, for example, to a back-surface irradiation type CMOS image sensor.

Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus

Solid-state imaging device and electronic apparatus

Imaging device and electronic device configured by bonding a plurality of semiconductor substrates including a first multilayer having a first vertical signal line formed in a differrent layer than the layer of a first wiring of a first connection region

A semiconductor device includes a flip-flop circuit, a control line, a first P-type transistor and a first non-volatile storage element, and a second P-type transistor and a second non-volatile storage element. The flip-flop circuit has a circular structure in which a first inverter circuit, a first connection line including a first node, a second inverter circuit, and a second connection line including a second node are coupled in order. The first P-type transistor and the first non-volatile storage element are coupled together in series between the first node and the control line. The second P-type transistor and the second non-volatile storage element are coupled together in series between the second node and the control line. The non-volatile storage element is a magnetic tunnel junction element including a pinned layer, a tunnel barrier layer, and a free layer arranged in order from a position close to the control line.

Semiconductor device including volatile and non-volatile memory

Growing community of inventors

Kanagawa, Japan

Hajime Yamagishi