Spansion Llc.

Hajime Wada

Jaeyong Park

Inkuk Kang

Cinti Xiaohua Chen

Boon-Yong Ang

Sameer S Haddad

Hiroyuki Kinoshita

Simon S Chan

Rinji Sugino

Hirokazu Tokuno

A method for forming a memory device is provided. A first layer is formed over a substrate. A second layer is formed over the first layer. A mask is formed over the second layer. Spacers are formed adjacent opposite sides of the mask. The second layer is etched to form at least one memory cell stack. The memory device is cleaned to remove the mask. A silicide region is formed within the second layer in the at least one memory cell stack, where the silicide region in each memory cell stack is bounded by the spacers.

System and method for gate formation in a semiconductor device

According to one exemplary embodiment, a structure in a semiconductor die comprises a metal pad situated in an interconnect metal layer, where the metal pad comprises copper. The structure further comprises an interlayer dielectric layer situated over the metal pad. The structure further comprises a terminal via defined in the interlayer dielectric layer, where the terminal via is situated on the metal pad. The terminal via extends along only one side of the metal pad. The structure further comprises a terminal metal layer situated on the interlayer dielectric layer and in the terminal via. The structure further comprises a dielectric liner situated on the terminal metal layer, where a bond pad opening is defined in the dielectric liner, and where the bond pad opening exposes a portion of the terminal metal layer. The interlayer dielectric layer is situated between the exposed portion of the terminal metal layer and metal pad.

Bond pad structure for copper metallization having increased reliability and method for fabricating same

A method for forming a memory device is provided. A memory cell stack is formed over a substrate. The memory cell stack includes a first layer formed over the substrate and a second layer formed over the first layer. A dielectric layer is formed over the first and second layers and the substrate. The dielectric layer is etched to expose at least an upper surface of the memory cell stack. The second layer is etched to recess the second layer with respect to an upper surface of the dielectric layer. A silicide region is formed on the second layer in the memory cell stack, where the silicide region in each memory cell stack is bounded by the dielectric layer extending above the upper surface of the memory cell stack.

According to one exemplary embodiment, a structure comprises a substrate. The structure further comprises at least one memory cell situated on the substrate. The structure further comprises a first interlayer dielectric layer situated over the at least one memory cell and over the substrate. The structure further comprises an oxide cap layer situated on the first interlayer dielectric layer. According to this exemplary embodiment, the structure further comprises an etch stop layer comprising TCS nitride situated on the oxide cap layer, where the etch stop layer blocks UV radiation. The structure further comprises a second interlayer dielectric layer situated on the etch stop layer. The structure may further comprise a trench situated in the second interlayer dielectric layer and the etch stop layer, where the trench is filled with copper. The structure may further comprise an anti-reflective coating layer situated on the second interlayer dielectric layer.

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Sunnyvale, CA, United States of America

Hajime Wada