Fujitsu Corporation

Hajime Takahashi

Akira Kabemoto

Hirohide Sugahara

Takatsugu Sasaki

Jun Funaki

Koji Suzuki

Toshihide Tsuzuki

Nobuhisa Hattori

Horihide Sugahara

Hideki Nakagawa

A single information processing device capable of configuring an information system that maintains matching between information retained by a self device and information retained by a partner device in a way that links up a plurality of information processing devices with each other, has a storage unit including a memory cell retaining a predetermined quantity of information and a comparing unit that compares the information retained by the memory cell at the present with information written afresh to the memory cell, an extraction unit extracting the information written afresh to the memory cell about which the comparing unit judges that the information retained at the present is different from the information written afresh, and a transmitting unit transmitting the extracted information to the partner device linking up with the self device.

Semiconductor storage device detecting change of memory content and information processing device including semiconductor storage device detecting change of memory content

A multiprocessor system having the capability of increasing the speed of a bus clock while retaining high reliability and fault tolerant performance as well as utilizing the current operating system resources. The multiprocessor system is made up of a plurality of processor modules connected together through a duplicated system bus. The duplicated system bus is divided into a plurality of segments, and these segments are coupled together by at least one bus extender mechanism. The multiprocessor system is also provided with first notification means which is provided between bus control mechanisms for controlling the states of physical buses and the bus extender mechanism, and the bus control mechanisms and the bus extender mechanism are mutually notified of the state of each mechanism through the first notification means.

Multiprocessor system connected by a duplicated system bus having a bus

A method of recovering an exclusive control instruction in a computer system having a plurality of processor modules and a plurality of shared memory modules which are coupled via a system bus. At least a part of the shared memory modules forms a dual construction. The exclusive control instruction makes access from an arbitrary one of the processor modules to the shared memory modules. First, a read access is performed to a master shared memory module from the arbitrary processor module in response to the exclusive control instruction. Thereafter, a write access is performed to a slave shared memory module, which forms a pair with the master shared memory module from the arbitrary processor module, so as to rewrite data in the slave shared memory module. Finally, a write access is performed to the master shared memory module from the arbitrary processor module, so as to rewrite data in the master shared memory module.

Method of recovering exclusive control instruction and multi-processor

An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a plurality of buffers coupled to the processor and to the system bus, and a controlling unit for writing data from the plurality of processors into the shared system memory module. Data is written into the shared system memory module by a processor generating write instructions to write data via the plurality of buffers and the system bus. The controlling unit controls the writing such that one writing instruction writes data into a plurality of buffers, then transfers the data to the shared system memory module via the system bus, with another writing instruction writing additional data into another plurality of buffers and transferring the additional data to the shared system memory module.

Asynchronous access system controlling processing modules making

Message control system specifying message storage buffer for data

An exclusive control system is provided in a system having a memory module and a plurality of processing modules sharing the memory module, each of the plurality of processing modules exclusively accessing the memory module while prohibiting other processing modules from accessing the memory module. The exclusive control system includes a determination unit for determining whether or not a process executed in response to an access request from a processor module among the plurality of processing modules is normally completed in the memory module, and a retry unit for, when the determination unit determines that the process executed in response to the access request is not normally completed, retrying the process while maintaining a state in which other processing modules are prohibited from accessing the memory module.

Multiprocessor system having a shared memory with exclusive access for a

Data communication for controlling message transmission and reception

A system bus control system for a system has a plurality of first modules and at least one second module. The first and second modules are connected together via a system bus which is controlled by an arbiter receiving requests to use the system bus from the first and second modules. Each of the first modules includes a lock control signal supervising unit, a lock control signal outputting unit, a command outputting unit and a response receiving unit. Each of the second modules includes a lock control signal supervising unit, a source module information storing unit, a command receiving unit and a response outputting unit. The lock control is controlled by the first and second modules rather than the arbiter, which permits one of the first and second modules to use the system bus if the system bus is idle.

Growing community of inventors

Kawasaki, Japan

Hajime Takahashi