Mitsubishi Electric Corporation

Tokyo Light Industry Co., Ltd.

Renesas Electronics Corporation

Kyoraku Co., Ltd.

Renesas Technology Corp.

Hitachi-johnson Controls Air Conditioning, Inc.

Hajime Sasaki

Masashi Sasaki

Satoshi Ichikawa

Takaaki Sakimura

Masashi Mizuochi

Masayoshi Horishima

Takashi Koshido

Naoki Muramatsu

Hirohiko Ito

Takanobu Naruse

Naoyuki Fushimi

Hiroki Kinoshita

Kazuho Hirao

Ryou Shibusawa

Shikiko Nachi

Yoichi Kinoshita

Kouji Yonekura

A sample () is created by cutting out a device on a plane (10-10). The device has a gate electrode () formed along a direction [2-1-10] on a plane c (0001) of a compound semiconductor () having a wurtzite structure. Edge dislocations having Burgers vectors of 1/3[2-1-10] and 1/3[−2110] and mixed dislocations having Burgers vectors of 1/3[2-1-13] and 1/3[−2113] are observed by making an electron beam () incident on the sample () from a direction [−1010] using a transmission electron microscope.

Crystal defect observation method for compound semiconductor

A test method for a semiconductor device comprising a substrate wafer (), in which an element is formed and a material through which an infrared ray can be transmitted, and a package having an airtight space () between a cap wafer (), which is provided opposite to the substrate wafer (); and which includes a water applying process in which the semiconductor device is exposed to a high moisture atmosphere and a leak discrimination process in which an infrared ray from the semiconductor device is detected and a leak of the package is discriminated based on absorption of the infrared ray by water molecules.

Test method of a semiconductor device and manufacturing method of a semiconductor device

In a method of producing a test-sample for a transmission electron microscope, it is so arranged that a massive body in a rectangular parallelepiped shape including a multiple quantum well active layer is cut out from a laser diode being a workpiece; thereafter, a test-sample is produced in which tilting oblique cutoff portions are formed at corner portions contiguously bordering on an upper surface of the massive body, so that surface-part active layers can be visually identified thereat; and thereafter, the test-sample is made thinner, and also an observation test-sample is cut out therefrom by taking on, as references, two surface-part active layers visually identifiable at the tilting oblique cutoff portions.

Method of producing test-sample for transmission electron microscope

A test method for a semiconductor device having a package with airtight space, which is formed between a substrate wafer on which an element is formed and a cap wafer which is provided being opposite to the substrate wafer, comprises an applying water process in which the semiconductor device is exposed to high moisture atmosphere and cooled and a leak discrimination process in which power is supplied to the element which is formed on the substrate wafer and leak of the package is discriminated by detecting a sound wave which is generated by the semiconductor device.

A semiconductor layer () is provided on a substrate (). A gate electrode (), a source electrode () and a drain electrode () are provided on the semiconductor layer (). A strongly correlated electron system material () is connected between the gate electrode () and the source electrode ().

Compound semiconductor device including MOTT insulator for preventing device damage due to high-energy particles

A semiconductor layer () is provided on a substrate (). A gate electrode (), a source electrode () and a drain electrode () are provided on the semiconductor layer (). A first passivation film () covers the gate electrode () and the semiconductor layer (). A source field plate () is provided on the first passivation film (), and extends from the source electrode () to a space between the gate electrode () and the drain electrode (). A second passivation film () covers the first passivation film () and the source field plate (). An end portion on the drain electrode () side of the source field plate () is curved to be rounded.

Method for manufacturing compound semiconductor device

In order to enable a drain pan to be visually checked for contamination without requiring a complicated operation, the present invention is configured so as to be equipped with: a housing; a drain pan provided inside the housing; a drain pump for pumping up drain water accumulated in the drain pan; an opening provided in a side surface of the housing; and a cover member attached to the opening and covering the opening. When the cover member is detached from the opening at least a portion of the drain pan can be viewed from the opening.

Drainage structure for air conditioner

In the container, when the cap is capped on the container opening portion, an inner wall surface of a cylindrical sub-fitting wall portion of the cap and an outer wall surface of a large diameter opening portion of the container opening portion closely contact each other, and an outer wall surface of a cylindrical main fitting wall portion of the cap and an inner wall surface of a small diameter opening portion of the container opening portion closely contact each other. In this way, pressing force that is applied to the outer wall surface of the cylindrical main fitting wall portion of the cap from the inner wall surface of the small diameter opening portion of the container opening portion is increased.

Container and cap

A semiconductor layer () is provided on a substrate (). A gate electrode (), a source electrode () and a drain electrode () are provided on the semiconductor layer (). A first passivation film () covers the gate electrode () and the semiconductor layer (). A source field plate () is provided on the first passivation film (), and extends from the source electrode () to a space between the gate electrode () and the drain electrode (). A second passivation film () covers the first passivation film () and the source field plate (). The first passivation film () has a quasi-conductive thin film () provided at least between the gate electrode () and the drain electrode () and having an electric resistivity of 1.0 &#x3a9;cm to 10&#x3a9;cm.

Compound semiconductor device

An annular protruding portion () is provided around an inner plug () at a radial interval on an annular horizontal wall portion () of a cap bodyBetween an annular flange portion () of the inner plug () and the annular protruding portion (), an annular accumulating groove portion () is provided. Particularly in the case of a liquid content, the liquid content may be scattered from within a cylindrical guide portion () when a lid member () is placed after use. The liquid content, however, is blocked by the annular protruding portion () and prevented from flowing further outward, while interfering with a top surface portion () and a cylindrical scattering suppression portion () of the lid member (). Thus, downward flow of the liquid content along the outer wall surface of the annular horizontal wall portion () of a main cap member () can be suppressed.

A method of manufacturing a nitride semiconductor device includes: forming a transistor having a gate electrode Schottky-joined to a nitride semiconductor layer; performing high-temperature annealing at a temperature of 200 to 360&#xb0; C. for 8 to 240 hours on the transistor; and after the high-temperature annealing, performing RF burn-in by applying radiofrequency power to the transistor at a channel temperature of 180 to 360&#xb0; C.

Method of manufacturing nitride semiconductor device

A cap body of a cap includes: a cylindrical inner wall section to be fitted into an inner wall surface of a container mouth section; an annular wall section that extends obliquely in an upper direction toward a radial-direction center integrally from an inner wall surface of the cylindrical inner wall section, has a lower wall surface of a truncated conical shape, and has a discharge hole in a radial-direction center portion; a check valve disposed above the annular wall section to open or close the discharge hole in such a manner that a valve section is detached from or seated on an annular valve seat around the discharge hole; and a guiding tubular body disposed above the check valve and having a discharge passage of contents from the discharge hole. Therefore, at the time of using the contents, the contents can be smoothly discharged to the outside.

A method of manufacturing a nitride semiconductor device, the nitride semiconductor device having an input terminal, a drain terminal, a gate terminal, and an output terminal, includes a burn-in step in which the nitride semiconductor device is heated while inputting an RF signal to the input terminal, applying a drain voltage to the drain terminal, and applying a gate voltage to the gate terminal. The burn-in step is continued until the nitride semiconductor device exhibits a decrease in gate current.

Method of manufacturing nitride semiconductor device, and burn-in apparatus

A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.

Semiconductor device and electronic device

A field-effect transistor includes a channel layer in which a two-dimensional electron gas is formed, an electron supply layer located on the channel layer, a source electrode located on the electron supply layer, a drain electrode located on the electron supply layer, a gate electrode located on the electron supply layer between the source electrode and the drain electrode, and an embedded layer embedded in the channel layer deeper than a two-dimensional electron gas region where the two-dimensional electron gas is formed, directly opposite an edge of the gate electrode on a side of the gate electrode toward the drain electrode. The embedded layer is a material that increases potential of the two-dimensional electron gas region.

Growing community of inventors

Tokyo, Japan

Hajime Sasaki