Yazaki Corporation

Hajime Okamoto

Satoshi Ishikawa

Masashi Sekizaki

Ryosuke Kawano

A plurality of result signals are driven low when abnormal condition is detected and driven high when no abnormal condition is detected. Presence and absence of the abnormal conditions of different types are indicated in a predetermined sequence by high and low signal levels of the result signals. The voltage detecting circuits simultaneously output the result signals on corresponding branching lines connected to a main line of a communication line. An OR gate outputs a result signal on which the result signals output by the voltage detecting circuits are superimposed. When at least one of the result signals of the voltage detecting circuits is at a level indicative of the presence of the abnormal condition, the OR gate outputs on the main line the result signal having the level indicative of the abnormal condition.

Abnormal condition detection apparatus

For providing a reliable voltage adjusting apparatus in low cost, a low-voltage control apparatus controls a high-voltage power supply circuit to be switched power off by transmitting a power-off signal through a second communication line arranged between the high-voltage power supply circuit and itself through an isolation unit when an information signal from an equalizing apparatus is not transmitted within a predetermined first malfunction judging period. The equalizing apparatus stops an equalizing process in itself when the information signal from the low-voltage control unit.

Voltage adjusting apparatus

A voltage detecting device for an on-vehicle high-voltage battery in which secondary batteries are connected in series, the on-vehicle high-voltage battery being divided into blocks each including at least one secondary battery, includes: voltage detecting means each assigned to each block for detecting a voltage of each secondary battery included in the block; and control means for controlling the voltage detecting means, wherein a common secondary battery is selected from the secondary batteries, a voltage of the common secondary battery being detectable by two voltage detecting means, wherein the control means causes the two voltage detecting means to detect the voltage of the common secondary battery, computes a detection error between the two voltage detecting means from the detected voltage values of the common secondary battery, and makes corrections in voltage values detected by the two voltage detecting means on the basis of the computed detection error.

Voltage detecting device

The battery control device includes: a state detecting means which receives electric power from an on-vehicle low-voltage battery having a supply voltage lower than that of an on-vehicle high-voltage battery composed of a plurality of unit cells connected together in series and detects a state of the on-vehicle high-voltage battery to monitor the on-vehicle high-voltage battery; an equalizing means for equalizing a voltage of each unit cell; and a control means which receives electric power from the on-vehicle low-voltage battery and starts to control the equalizing means in response to turning-off of an ignition switch, wherein the control means cuts electric power supplied from the on-vehicle low-voltage battery to the state detecting means after the turning-off of the ignition switch and before the control means starts to control the equalizing means.

Battery control device for equalization of cell voltages

The present invention is to provide a voltage detector having a common communication line for reducing a manufacturing cost. A low voltage line CPU transmits a detection instruction including an assignment of one address among a plurality of blocks. The detection instruction is branched by a transmitting bus line for concurrently transmitting to a plurality of voltage detector units. When one of the voltage detector units receives the detection instruction with the address being same as a self-address thereof, the voltage detector unit detects output voltages of unit cells and transmits the detected result to the low voltage line CPU. When the received address is not the self-address, the voltage detector unit does not transmit the detected result.

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Shizuoka, Japan

Hajime Okamoto