Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Hajime Ogawa

Taketo Heishi

Shuichi Takayama

Tetsuya Tanaka

Nobuo Higaki

Shohei Michimoto

Toshiyuki Sakata

Kensuke Odani

Ryoko Miyachi

Shinya Miyaji

Kenichi Kawaguchi

Teruo Kawabata

Hazuki Okabayashi

Takeshi Tanaka

Shuji Miyasaka

Tokuzo Kiyohara

Hideshi Nishida

Yasuhiro Yamamoto

Tomoo Hamada

Tomokazu Ishikawa

Masaki Maeda

Tsuneyuki Suzuki

Kiyohiko Sumida

Katsuhiro Okuno

Hirotetsu Tomita

Masato Suzuki

Yukihiro Sasagawa

Takenobu Tani

Manabu Kuroda

Yoshihiro Koga

Kiyoshi Nakashima

Masatsugu Daimon

Kyoko Hattori

Kenji Hattori

A compiler apparatus, which can perform software pipelining optimization that has a considerable effect of reducing the number of execution cycles taken to complete a loop process, converts a source program into a machine program for a processor which is capable of parallel processing. The compiler apparatus is composed of: a parsing unit operable to parse the source program and then to convert the source program into an intermediate program which is described in an intermediate language; an optimization unit operable to optimize the intermediate program; and a conversion unit operable to convert the optimized intermediate program into the machine language program, wherein the optimization unit is operable to execute software pipelining, by inserting a transfer instruction, which is used for transferring data between operands, into a loop process included in the intermediate program so that a data dependence relation is changed.

Compiler apparatus

A compiler comprises an analysis unit that detects directives (options and pragmas) from a user to the compiler, an optimization unit that is made up of a processing unit (a global region allocation unit, a software pipelining unit, a loop unrolling unit, a 'if' conversion unit, and a pair instruction generation unit) that performs individual optimization processing designated by options and pragmas from a user, following the directives and the like from the analysis unit, etc. The global region allocation unit performs optimization processing, following designation of the maximum data size of variables to be allocated to a global region, designation of variables to be allocated to the global region, and options and pragmas regarding designation of variables not to be allocated in the global region.

Compiler apparatus with flexible optimization

A program re-writing method which re-writes an inputted program into a program for a processor for controlling whether or not a process is executed based on a yes or no execution flag, said program re-writing method including: inserting a comparison process into the inputted program, the comparison process comparing first address information, which is memory address information accessed by a first memory access process included in the inputted program, and second address information, which is address information of a memory accessed by a second memory access process included in the inputted program, and writing a comparison result into the yes or no execution flag; and inserting a yes or no execution flag-attached logic preservation process into the inputted program, the yes or no execution flag-attached logic preservation process being a process executed based on a value of the yes or no execution flag and preserving the same result as a result of the inputted program when executed.

Program re-writing apparatus

An operator definition fileand the like included in a source programand a compilerthat translates the source programinto a machine language programare provided. The operator definition fileincludes definitions of various fixed point type operators by class definitions. The compilercan generate effectively advanced and specific instructions that a processor executes and make improvements through expanding functions and the like without repeating frequently upgrading of the version of the compiler itself. The compileris made up of an intermediate code generation unitthat generates intermediate codes, a machine language instruction substitution unitthat substitutes the intermediate codes referring to classes defined by the operator definition filewith machine language instructions and an optimization unitthat performs optimization targeting the intermediate codes including the substituted machine language instructions.

Compiler, compiler apparatus and compilation method

A compiler apparatus that improves the performance of loop processing. The compiler apparatus translates a C program that includes a loop into a machine language program, and includes: a movement judgment unit that judges whether or not an instruction which is positioned outside of the loop of the C program can be moved into the loop, based on a state of live ranges of variables used in the instruction; a movement execution unit that moves the instruction into the loop in the case where the movement judgment unit judges that the instruction can be moved into the loop, thereby generating an intermediate program; and a translation unit that translates the intermediate program into the machine language program.

When a branch instruction is decoded by the instruction decoders, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculatorand the lower 3 bits are sent to the lower PC calculator. The lower PC calculatoradds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PCand sends the result to the lower PCas the updated lower PC. The upper PC calculatoradds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC, and a carry that may be received from the lower PC calculator, and sends the result to the upper PCas the updated upper PC.

Processor for executing instructions in units that are unrelated to the units in which instructions are read, and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor

In order to overcome the problem that conditionally executed instructions are executed as no-operation instructions if their condition is not fulfilled, leading to poor utilization efficiency of the hardware and lowering the effective performance, the processor decodes a number of instructions that is greater than the number of provided computing units and judges their execution conditions with an instruction issue control portion before the execution stage, Instructions for which the condition is false are invalidated, and subsequent valid instructions are assigned so that the computing units (hardware) is used efficiently. A compiler performs scheduling such that the number of instructions whose execution condition is true does not exceed the upper limit of the degree of parallelism of the hardware. The number of instructions arranged in parallel at each cycle may exceed the degree of parallelism of the hardware.

Processor, compiler and compilation method

A compiler capable of increasing the hit rate of the cache memory is provided that targets a computer having a cache memory, and that converts a source program into an object program. The compiler causes a computer to analyze group information that is used for grouping data objects included in the source program, and places the data objects into groups based on a result of the analysis. The compiler also causes the computer to generate an object program based on a result of the grouping, where the object program does not allow data objects belonging to different groups to be laid out in any blocks with the same set number on the cache memory.

Compiler apparatus and linker apparatus

A processor according to the present invention includes a decoding unit, an operation unitand others. When the decoding unitdecodes Instruction vcchk, the operation unitand the like judges whether vector condition flags VC&#x2dc;VC() of a condition flag register (CFR)are all zero or not, and (i) sets condition flags Cand Cof the condition flag register (CFR)to 1 and 0, respectively, when all of the vector condition flags VC&#x2dc;VCare zero, and (ii) sets the condition flags Cand Cto 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC&#x2dc;VCare stored in the condition flags C&#x2dc;C

Processor executing SIMD instructions

A compiler, which is a compiler that realizes program development in a fewer man hours, translates a source programwritten in a high-level language into a machine language program. This compileris comprised of: a directive obtainment unit that obtains a directive that a machine language program to be generated should be optimized; a parser unitthat parses the source program; an intermediate code conversion unitthat converts the source programinto intermediate codes based on a result of the parsing performed by the parser unit; an optimization unitthat optimizes the intermediate codes according to the directive; and a code generation unitthat converts the intermediate codes into the machine language program. The above directive is a directive to optimize the machine language program targeted at a processor that uses a cache memory.

Compiler apparatus for optimizing high-level language programs using directives

A compiler apparatus is capable of generating instruction sequences causing a processor to operate with lower power consumption. The compiler apparatus translates a source program into a machine language program for a processor including execution units which can execute instructions in parallel, and including instruction issue units which issue the instructions executed, respectively, by the execution units. The compiler apparatus includes a parser unit operable to parse the source program, an intermediate code conversion unit operable to convert the parsed source program into intermediate codes, an optimization unit operable to optimize the intermediate codes to reduce a hamming distance between instructions from the same instruction issue unit in consecutive instruction cycles, and includes a code generation unit operable to convert the optimized intermediate codes into machine language instructions.

Compiler apparatus and method of optimizing a source program by reducing a hamming distance between two instructions

The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction 'jloop C,C:C,TAR,Ra', the processor (i) sets a conditional flag Cto 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag Cto a conditional flag C, moves the value of a conditional flag Cto the conditional flag C, and moves the value of the conditional flag Cto the conditional flags Cand C, (iii) adds &#x2212;1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.

Processor and compiler for decoding an instruction and executing the decoded instruction with conditional execution flags

A compiler apparatus enables description of a particular hardware module in the existing programming language, although the description has not been possible in hardware designing to input programming language. In the header file, a particular hardware indescribable in programming language is defined. And the compiler apparatus includes a parser unitanalyzing syntax of source program, an intermediate code converting unitconverting the syntactically analyzed source programto an intermediate code and code generating unitconverting the intermediate code to the RTL description. The intermediate code converting unitincludes a detecting unitdetecting a particular hardware defined in the header fileout of the source programand a replacing unitreplacing the detected particular hardware in the detecting unitwith the intermediate code corresponding to a particular hardware.

Growing community of inventors

Suita, Japan

Hajime Ogawa