Nakamichi Corporation

Hajime Obinata

Akira Imamura

A D/A converter divides an input digital data into at least two overlapping digital ranges. The data in the two ranges are converted separately from digital to analog by a low-range and a high-range DAC. The resulting analog signals are then added with a weighting that maintains the proper loudness relationships in the final combined analog output. In a low range of amplitudes, only the low-range DAC performs D/A conversion. Above a predetermined amplitude threshold, some of the high significant bits to the low-range DAC are frozen, while a remaining low significant bits of the low-range DAC are permitted to vary with the input digital data. Above the predetermined amplitude threshold, a digital value is subtracted from the data fed to the high-range DAC. The subtracted value is equal to the frozen value in the low-range DAC. In some embodiments, one or more supplementary bits are developed to smooth the transition between ranges. In other embodiments, more than two DACs receive overlapping ranges of the input digital data. In some of the embodiments, positive and corresponding negative analog representations of the ranges are connected in push-pull.

Digital/analog converter

A digital-analog converter circuit comprising a current output type digital-analog converter and a current/voltage converter connected to an output terminal of the current output type digital/analog converter, the current/voltage converter including bias application means to always apply a bias voltage having a predetermined set value to the output terminal of the digital/analog converter.

Digital-analog conversion circuit with application of voltage biasing

A deglitching circuit suppresses a glitch occurring on an output of a digital/analog converting circuit. The deglitching circuit comprises a detector for detecting a status change that will generate the glitch, of digital data to be inputted into the digital/analog converting circuit, a generator for generating in response to an output of the detector a deglitching pulse for suppressing the glitch, and an operation circuit for canceling with the use of the deglitching pulse the glitch occurring on the output of the digital/analog converting circuit converted from the digital data.

Deglitching circuit

A digital/analog converting device comprises a first digital/analog converter for converting upper M bits of an input digital signal into a first analog signal; a memory for receiving, as address data, at least a digital signal of lower N bits of the input digital signal to output lower-bit-output-approximate data of S (S&gt;N) bits in response to the address data; a second digital/analog converter for converting digital data at least including the S-bit lower-bit-output-approximate data into a second analog signal; and an analog adder for outputting an added analog signal obtained by adding the first and second analog signals at a predetermined ratio. The S-bit lower-bit-output-approximate data are set such that, supposing a level change of the added analog signal with respect to a change of an LSB of the upper M bits being .DELTA.L, a minimum step increase of the digital signal of lower N bits causes a level of the added analog signal to increase by about .DELTA.L/2.sup.N.

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Kodaira, Japan

Hajime Obinata