Tokyo Electron Limited

Hajime Nakabayashi

Yumiko Kawano

Koji Akiyama

Tadahiro Ishizaka

Junichi Kitagawa

Hiroki Murakami

Ryuichi Asako

Takuya Sugawara

Genji Nakamura

Yoshihiro Hirota

Shuji Azumo

Yusaku Kashiwagi

Kenichi Oyama

Takashi Kobayashi

Michitaka Aita

Tetsuya Shibata

Yasushi Akasaka

Yoshitsugu Tanaka

Kazuki Yamada

Philippe Gaubert

Tomohito Yamaji

A pattern formation method includes: forming a photosensitive hard mask made of a transition metal oxide film on a surface of a substrate; exposing the photosensitive hard mask to EUV light in a desired pattern; causing a state change in an exposed region by heat generated during exposure; and selectively removing either a region where the state change has occurred or a region where the state change has not occurred.

Pattern formation method and photosensitive hard mask

A method of manufacturing a semiconductor device includes a first laminating step, a second laminating step, a third laminating step, a first annealing step, and a fourth laminating step. In the first laminating step, a first electrode film is laminated on a substrate. In the second laminating step, a capacitive insulator is laminated on the first electrode film. In the third laminating step, a metal oxide is laminated on the capacitive insulator. In the first annealing step, the first electrode film, the capacitive insulator, and the metal oxide, which are laminated on the substrate, are annealed. In the fourth laminating step, a second electrode film is laminated on the annealed metal oxide. The capacitive insulator is an oxide that contains at least one of zirconium and hafnium, and the metal oxide is an oxide that contains at least one of tungsten, molybdenum, and vanadium.

Method of manufacturing semiconductor device

There is provided a semiconductor device including: a first wiring; a second wiring; a dielectric layer configured to insulate the first wiring and the second wiring from each other; and an impedance adjustment layer formed between the first wiring and the second wiring, and configured to adjust an impedance between the first wiring and the second wiring.

Semiconductor device

A method of selectively forming a thin film on a substrate to be processed in which a conductive film and an insulating film are exposed to a surface of the substrate includes: selectively forming a first Ru film only on a first surface, which is an exposed surface of the conductive film and formed of one of Ru, RuO, Pt, Pd, CuO, and CuO, using an Ru(EtCp)gas and an Ogas; and selectively forming a first SiO-containing insulating film only on a second surface, which is an exposed surface of the insulating film has OH groups, by performing one or more times a process of supplying a TMA gas to the substrate to adsorb TMA only to the second surface and a process of forming an SiOfilm only on a surface of the adsorbed TMA using a silanol group-containing silicon raw material and an oxidizing agent.

Selective film forming method and method of manufacturing semiconductor device

A phase change memory includes an insulating layer on a substrate, an electrode layer having one pole and an electrode layer having another pole within the insulating layer, an opening portion whose lower portion on an upper portion of the insulating layer is substantially square or substantially rectangular, a phase change portion formed substantially parallel to a surface of the substrate along the respective sides of the lower portion of the opening portion, and two connection electrodes having a pole and connected to the phase change portion at two opposing corners of the lower portion of the opening portion connecting a diode portion connected to the electrode layer having one pole and the phase change portion, and two connection electrodes having another pole and connected to the phase change portion at the other two opposing corners connecting the phase change portion and the electrode layer having another pole.

Phase change memory and method for fabricating phase change memory

The memory apparatus includes a memory device including a gate insulating layer formed on a silicon substrate by sequentially stacking a tunnel oxide layer, a charge trap layer, and a block oxide layer in this order, on the silicon substrate. In addition, a gate electrode is formed on the gate insulating layer. The block oxide layer is formed by stacking a first block oxide layer and a second block oxide layer, wherein the first block oxide layer is adjacent to the charge trap layer and the second block oxide layer is adjacent to the gate electrode. The second block oxide layer is formed of a dielectric material having higher permittivity than that of the first block oxide layer and having higher electron affinity than that of the first block oxide layer.

Memory apparatus

A method for manufacturing a fin-type field effect transistor simply and securely by using a SOI (Silicon On Insulator) wafer, capable of suppressing an undercut formation, is disclosed. The method includes forming a fin-shaped protrusion by selectively dry-etching a single crystalline silicon layer until an underlying buried oxide layer is exposed; forming a sacrificial oxide film by oxidizing a surface of the protrusion including a damage inflicted thereon; and forming a fin having a clean surface by removing the sacrificial oxide film by etching, wherein an etching rate rof the sacrificial oxide film is higher than an etching rate rof the buried oxide layer during the etching.

Manufacturing method of fin-type field effect transistor

Growing community of inventors

Tokyo, Japan

Hajime Nakabayashi