Semiconductor Energy Laboratory Co., Ltd.

Other

Hajime Kimura

Shunpei Yamazaki

Atsushi Umezaki

Jun Koyama

Hideki Uochi

Yu Yamazaki

Yoshifumi Tanada

Yasunori Yoshida

Yasuko Watanabe

Hideaki Kuwabara

Atsushi Miyaguchi

Hideaki Shishido

Yutaka Shionoiri

Yukie Suzuki

Yoshiyuki Kurokawa

Keisuke Miyagawa

Kiyoshi Kato

Mitsuaki Osame

Tatsunori Inoue

Aya Anzai

Yasuhiro Jinbo

Masato Yonezawa

Satoshi Seo

Takayuki Ikeda

Tatsuya Onuki

Ryota Fukumoto

Hitoshi Kunitake

Masafumi Morisue

Kengo Akimoto

Toshinari Sasaki

Masashi Tsubuku

Takanori Matsuzaki

Hiroyuki Miyake

Yasuyuki Arai

Osamu Nakamura

Shinji Maekawa

Rumo Satake

Toru Takayama

Satoshi Murakami

Satoru Okamoto

Mai Akiba

Takahiro Fukutome

Masahiko Hayakawa

Yoshiaki Oikawa

Koji Dairiki

Yuta Endo

Hiromi Yanai

Hiroki Ohara

Tetsuji Ishitani

Yoshiaki Ito

Takuro Ohmaru

Junichi Koezuka

Kenichi Okazaki

Masami Jintyou

Yasuharu Hosaka

Gen Fujii

Daisuke Kurosaki

Junpei Sugao

Takahiro Iguchi

Kentaro Hayashi

Naoto Goto

Yoshiharu Hirakata

Kei Takahashi

Hideto Ohnuma

Hisao Ikeda

Daisuke Kubota

Yuki Okamoto

Hiroko Abe

Yasumasa Yamane

Tomoyuki Iwabuchi

Saishi Fujikawa

Tsutomu Murakawa

Kosei Nei

Makoto Yanagisawa

Hiroaki Honda

Hiromi Sawai

Junichiro Sakata

Hidekazu Miyairi

Takeshi Nishi

Koji Kusunoki

Hiromichi Godo

Takeshi Osada

Kensuke Yoshizumi

Daisuke Matsubayashi

Tomoaki Atsumi

Hidetomo Kobayashi

Kazutaka Inukai

Shou Nagao

Kiyofumi Ogino

Satoshi Kobayashi

Ryo Tokumaru

Yoshinori Ieda

Teruyuki Fujii

Hiroki Dembo

Haruyuki Baba

Satoshi Shinohara

Kiyotaka Kimura

Kazuki Tsuda

Takeya Hirose

Miki Suzuki

A semiconductor device where delay or distortion of a signal output to a gate signal line in a selection period is reduced is provided. The semiconductor device includes a gate signal line, a first and second gate driver circuits which output a selection signal and a non-selection signal to the gate signal line, and pixels electrically connected to the gate signal line and supplied with the two signals. In a period during which the gate signal line is selected, both the first and second gate driver circuits output the selection signal to the gate signal line. In a period during which the gate signal line is not selected, one of the first and second gate driver circuits outputs the non-selection signal to the gate signal line, and the other gate driver circuit outputs neither the selection signal nor the non-selection signal to the gate signal line.

Semiconductor device

A semiconductor device that has reduced power consumption and is capable of non-destructive reading is provided. The semiconductor device includes a first circuit including a first transistor and a first FTJ element, and a second circuit including a second transistor and a second FTJ element. A first terminal of the first transistor is electrically connected to an output terminal of the first FTJ element, and a first terminal of the second transistor is electrically connected to an input terminal of the second FTJ element. A second terminal of the first transistor and a second terminal of the second transistor are electrically connected to a read circuit. In a data writing method, a voltage is applied between the input terminal and the output terminal of each of the first FTJ element and the second FTJ element to polarize the first FTJ element and the second FTJ element. In a data reading method, a differential current flowing through the first FTJ element and the second FTJ element is input to the read circuit.

Semiconductor device with first and second elements and electronic device

To provide a novel input/output panel that is highly convenient or reliable, a novel input/output device that is highly convenient or reliable, a novel input/output panel, a novel input/output device, or a novel semiconductor device. The input/output panel includes a pixel, a sensor element, a signal line, a control line, and a scan line. The sensor element has a region overlapping with the pixel. The signal line is electrically connected to the sensor element and the pixel. The control line is electrically connected to the sensor element. The scan line is electrically connected to the pixel.

Input/output panel and input/output device

A novel semiconductor device is provided. A component extending in a first direction, and a first conductor and a second conductor extending in a second direction are provided. The component includes a third conductor, a first insulator, a first semiconductor, and a second insulator. In a first intersection portion of the component and the first conductor, the first insulator, the first semiconductor, the second insulator, a second semiconductor, and a third insulator are provided concentrically. In a second intersection portion of the component and the second conductor, the first insulator, the first semiconductor, the second insulator, a fourth conductor, and a fourth insulator are provided concentrically around the third conductor.

Semiconductor device and electronic device

A semiconductor device with low power consumption is provided. In a cascode circuit including a first transistor provided on a low power supply potential side and a second transistor provided on a high power supply potential side, a source or a drain of a third transistor and a capacitor are connected to a gate of the second transistor. A gate of the first transistor is electrically connected to a back gate of the second transistor. An OS transistor is used as the third transistor.

A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits each have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When a potential corresponding to second data is input to each of the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring. The currents output from the first and second circuits to the first wiring or the second wiring are determined in accordance with the first and second potentials held at the first and second holding nodes.

To improve viewing angle characteristics by varying voltage which is applied between liquid crystal elements. A liquid crystal display device in which one pixel is provided with three or more liquid crystal elements and the level of voltage which is applied is varied between the liquid crystal elements is varied. In order to vary the level of the voltage which is applied between the liquid crystal elements, an element which divides the applied voltage is provided. In order to vary the level of the applied voltage, a capacitor, a resistor, a transistor, or the like is used. Viewing angle characteristics can be improved by varying the level of the voltage which is applied between the liquid crystal elements.

Liquid crystal display device

A novel display panel that is highly convenient or reliable is provided. The display panel includes a first pixel, a second pixel, and a functional layer. The first pixel includes a first display element, and the second pixel includes a second display element. The functional layer includes a first pixel circuit and a second pixel circuit. The first display element includes a first electrode, a second electrode, and a layer containing a liquid crystal material. A first distance is provided between the first electrode and the functional layer. A second distance is provided between the second electrode and the functional layer. The first electrode and the second electrode each include a region overlapping with the layer containing a liquid crystal material. The second distance is shorter than the first distance. The second display element includes a third electrode, a fourth electrode, and the layer containing a liquid crystal material. A third distance is provided between the third electrode and the functional layer. A fourth distance is provided between the fourth electrode and the functional layer. The fourth distance is shorter than the third distance and longer than the first distance.

Display panel, display device, input/output device, and data processing device

An input/output device includes a first sensor electrode and a second sensor electrode. In addition, the input/output device includes a first electrode and a second electrode which are electrodes for a display element, and a substrate sandwiched between the first sensor electrode and the second sensor electrode. The second sensor electrode is formed concurrently with the first electrode using the same material. The input/output device sensors a change in capacitance of a capacitor formed between the first sensor electrode and the second sensor electrode. Furthermore, a third sensor electrode to which a floating potential is applied may be provided to overlap with the first electrode. In the input/output device, either a liquid crystal element or a light-emitting element may be used, or both the liquid crystal element and the light-emitting element may be used.

Input/output panel, input/output device, and semiconductor device

To suppress a malfunction of a circuit due to deterioration in a transistor. In a transistor which continuously outputs signals having certain levels (e.g., L-level signals)

A semiconductor device with low power consumption that is capable of non-destructive reading is provided. The semiconductor device includes a first transistor, a second transistor, a third transistor, a first FTJ element, and a second FTJ element. A first terminal of the first transistor is electrically connected to an output terminal of the first FTJ element, an input terminal of the second FTJ element, and a gate of the second transistor. A first terminal of the second transistor is electrically connected to a second terminal of the third transistor. For data writing, polarization is caused in each of the first FTJ element and the second FTJ element in accordance with data. For data reading, a voltage that does not cause a change in polarization is applied between the input terminal of the first FTJ element and the output terminal of the second FTJ element, a potential is supplied to the gate of the second transistor, and a current or voltage corresponding to data is obtained from the first terminal of the second transistor.

A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. The first conductor is provided with a first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

Memory device

A touch panel which is thin, has a simple structure, or is easily incorporated into an electronic device is provided. The touch panel includes a first substrate, a second substrate, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, liquid crystal, and an FPC. The first conductive layer has a function of a pixel electrode. The second conductive layer has a function of a common electrode. The third and fourth conductive layers each have a function of an electrode of a touch sensor. The FPC is electrically connected to the fourth conductive layer. The first, second, third, and fourth conductive layers and the liquid crystal are provided between the first and second substrates. The first, second, and third conductive layers are provided over the first substrate. The FPC is provided over the first substrate.

Display device

A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting second electrode provided over the substrate; a light-transmitting semiconductor layer provided so as to be electrically connected to the first electrode and the second electrode; a first wiring electrically connected to the first electrode; an insulating layer provided so as to cover at least the semiconductor layer; a light-transmitting third electrode provided over the insulating layer in a region overlapping with the semiconductor layer; and a second wiring electrically connected to the third electrode.

Semiconductor device and method for manufacturing the same

An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included.

Semiconductor device including storage capacitor having pixel electrode, directly stacked conductive layer, and insulating layer interposed between them, wherein the stacked conductive layers extending towards the gate and source wirings/lines

Growing community of inventors

Kanagawa, Japan

Hajime Kimura