Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi Hokkai Semiconductor Ltd.

Hitachi, Ltd.

Renesas Northern Japan Semiconductor, Inc.

Renesas Semiconductor Package & Test Solutions Co., Ltd.

Hitachi Vlsi Engineering Corp.

Other

Hitachi Cable, Inc.

Hajime Hasebe

Tadatoshi Danno

Yukihiro Satou

Kenji Amano

Atsushi Fujisawa

Hiromichi Suzuki

Gen Murakami

Kanji Otsuka

Takayuki Okinaga

Takashi Emata

Osamu Horiuchi

Yuuji Shirai

Makoto Aida

Toshiyuki Shinya

Motoya Ishida

Yasuhiro Kashimura

Yoichi Kinouchi

Syuudai Fukaya

In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

Semiconductor device

The outflow of die bond material is prevented and the quality and reliability of a semiconductor device are improved. A tab, a plurality of leads arranged around the tab, silver paste arranged on a chip supporting surface of the tab, and a semiconductor chip mounted via silver paste on the tab are included. Further, a plurality of wires which electrically connect a pad of the semiconductor chip, a lead, and a sealing body which does the resin seal of the semiconductor chip and the wires are also included. By forming a step part whose height is lower than the chip supporting surface at an edge part of the chip supporting surface of the tab, the silver paste protruded from the tab can be stopped at the step part. As a result, an outflow to the back surface of the sealing body of silver paste can be prevented.

Semiconductor device and manufacturing method of the same

According to the method of manufacturing a semiconductor device, a lead frame is provided wherein the thickness of a tab-side end portion of a silver plating for wire connection formed on each suspending leadis smaller than that of a silver plating formed on each lead. Thereafter, a semiconductor chip is mounted onto a tab. In this case, since the entire surface of the silver plating on the suspending leadis in a crushed state, it is possible to prevent contact of the semiconductor chip with the silver plating when mounting the chip onto the tab. Consequently, in a die bonding process, the semiconductor chip can slide on the tab without contacting the silver plating and thereby making it possible to diminish damage to the semiconductor chip when mounted onto the tab and hence to possibly prevent cracking or chipping of the chip when assembling the semiconductor device.

Method of manufacturing a semiconductor device

Semiconductor device having a chip mounting portion and a plurality of suspending leads supporting the chip mounting portion and each suspension lead having a bent portion

A semiconductor device with improved reliability is provided. The semiconductor device in a QFN package configuration has a semiconductor chip mounted on a tab, leads which are alternately arranged around the tab and electrically connected to the electrodes of the semiconductor chip via bonding wires, and an encapsulating resin portion for encapsulating therein the semiconductor chip and the bonding wires. The lower exposed surfaces of the leads are exposed at the outer peripheral portion of the back surface of the encapsulating resin portion to form external terminals. The lower exposed surfaces of the leads are exposed at the portion of the back surface of the encapsulating resin portion which is located inwardly of the lower exposed surface of the leads to also form external terminals. The cut surfaces of the leads are exposed at the cut surfaces of the encapsulating resin portion, while the upper exposed surfaces of the leads are exposed from the portion of the encapsulating resin portion which is proximate to the cut surfaces thereof. Each of the upper exposed surfaces of the leads has a width smaller than the width of each of the lower exposed surfaces thereof.

Semiconductor package configuration with improved lead portion arrangement

A semiconductor device improved in packaging reliability is disclosed. Each of leads used in the semiconductor device has a first surface positioned between a main surface of a resin sealing body and a back surface opposite to the main surface of the resin sealing body, a second surface positioned on the side opposite to the first surface and exposed from the back surface of the resin sealing body, a first end face positioned on a semiconductor chip side, a second end face positioned on the side opposite to the first end face and exposed from a side face of the resin sealing body, and a recessed portion depressed from the second surface to the first surface side and contiguous to the second end face, the second surface and an inner wall surface of the recessed portion being covered with a plating layer which is higher in solder wettability than the second end face of each of the leads.

Growing community of inventors

Hakodate, Japan

Hajime Hasebe