Mitsubishi Denki Kabushiki Kaisha

Matsushita Electric Industrial Co., Ltd.

Sanyo Electric Co., Ltd.

Sharp Kabushiki Kaisha Corporation

Sharp Corporation

Hajime Asano

Hiroaki Terada

Kenji Shima

Katsuhiko Asada

Masahisa Shimizu

Shinji Komori

Hiroaki Nishikawa

Souichi Miyata

Hiroki Miura

Satoshi Matsumoto

Mitsuo Meichi

Soichi Miyata

Niroaki Nishikawa

Toshiya Okamoto

Kouji Miyao

Shuji Hara

Katushiko Asada

An associative storage comprises two data transmission paths each of which includes a self-running shift register formed in loop fashion. In the respective data transmission paths, data packets each having identification data are transmitted to respective stages of the shift register. The identification data are extracted from the data packets transmitted on the shift registers and compared with each other in a comparing circuit. If and when the identification data of two data packets respectively transmitted on the respective transmission paths are coincident, those two data packets are determined as the data packets to be paired. The data packet pair is read from the data transmission paths.

Associative storage for data packets including asynchronous,

An operator can use a word processor for editing by substituting character strings. The operator can use a designating part of the word processor to identify what portion of a text is to be edited. The portion of the text to be edited is a designated character string. A plurality of substitute strings can be stored in a memory. The substitute character strings can replace the designated character strings. In addition, the designated character string can be placed in a memory to be used later as a substitutive character string.

Word processor with operator inputted character string substitution

A data transmission apparatus for transmitting data between systems includes: an input data transmission path, an output data transmission path, and a branch data transmission path each constituted by a shift register, each data transmission path has a plurality of data storage circuits and a plurality of transfer control circuits each provided corresponding to each o--stage. The data storage circuit control a self stage data storage circuit in accordance with a control signal from the transfer control circuit of an adjacent stage. An initialization circuit for initializing the device is provided so that data on the data transmission path does not remain at the start of operation of the device.

Data transmission apparatus

By providing a tag data renewing unit in a data flow-computer, the 'delay' function, which is necessary for a digital filter, etc., can be realized, and it is unnecessary to keep the order relation for tokens with respect to first-in/first-out, which must be kept at respective points in a conventional data flow computer, and thereby the architecture of a compiler can be simplified and at the same time the execution time can be shortened.

Information processing apparatus for a data flow computer

A data processing apparatus includes two data transmission paths formed likewise in a loop fashion. These data transmission paths include a plurality of latch registers connected in a cascade fashion respectively and are constituted as a so-called self-running type shift register wherein each data word constituting a data packet is shifted in sequence provided that a pre-stage register is vacant. Data packets are transmitted in the directions reverse to each other on the two loop-shaped data transmission paths an identification data included in each data packet being transmitted is detected in a section defined as a data packet pair detecting section. The detected identification data are compared in a comparing circuit and, one new data packet is produced from the two data packets in a manner that a data packet is joined from one data transmission path to the other data transmission path.

System containing loop shaped transmission paths for transmitting data

In a data transmission apparatus, a plurality of data processing modules are used and required sequence setting is performed to a port sequencer of input/output ports of each data processing module, and the daisy chain transfer of the selective data transfer, the load distribution data transfer, the collective data transfer is combined between the data processing modules, thereby the data transmission is performed efficiently at high speed.

Data transmission apparatus having cascaded data processing modules for

A data processing apparatus includes a self-running type shift register and this shift register includes a plurality of latch registers arranged in a cascade fashion. The latch register latches a data packet on a word basis. In each latch register, a coincidence element is disposed in association therewith and these coincidence elements allow transfer of data from a post-stage latch register provided that a pre-stage latch register is vacant. A data processing element is installed between two latch registers and the data processing element processes operand data from either or both of the two latch register in response to the kind of processing shown by an operation code comprised in the preceding word. The result of processing is transferred to the pre-stage latch register when the pre-stage latch register is placed in the vacant state under control of the coincidence element.

Processing system using cascaded latches in a transmission path for both

In an information processor, input interface units (161, 162) are connected to one ring data bus (191) through jointing units (201, 202) and data processing units (181 and 185) are connected to the ring data bus (191) through jointing units (203 through 206) and branching units (221 through 224). Data processing units (183 through 187) are connected to the other ring data bus (192) through jointing units (207 through 210) and branching units (225 through 228) and output interface units (171, 172) are connected to the other ring data bus (192) through branching units (229, 230). The ring data buses (191, 192) propagate the respective in data through the input interface units (161, 162) while storing such data, and processing the data in any of the data processing units to provide outputs to any of the output interface units (171, 172). Thus, since the data is transmitted through the ring data buses ( 191, 192) while being held in the data buses, there is no necessity to provide a memory for temporarily storing the data in each data processing unit. In addition, for a large scale integration of a system, it is easy to integrate each unit in a high density.

Information processor capable of data transfer among plural digital data

A data transmission system comprises an input data transmission line (1), an output data transmission line (4), a branching data transmission line (5) and a jointing data transmission line (7) formed respectively by asynchronous free-running shift registers using a plurality of data latches (101 to 106, 401 & 402, 501 & 502, 701 & 702) and, C elements (111 to 116, 411 & 412, 511 & 512, 711 & 712) respectively. A branching control circuit 3 supplies data to be branched to the branching data transmission line (5) in response to the decision by a branching decision circuit (2) as to the fact that the data to be branched is transmitted on the input data transmission line (1). A jointing control circuit (6) supplies data to be joined to the output data transmission line (4) in response to the decision by an empty buffer verifier (8) as to the nonexistence of data in the input data transmission line (1) and the output data transmission line (4) when the data to be jointed is transmitted on the jointing data transmission line (7). Thus, the data transmission system has branching and jointing functions and if it is used as a constituent of a network, data can be transmitted among asynchronous systems.

Data transmission line branching system

A tag data processing apparatus is described for use in a data flow computer utilizing a tagged token scheme. A tag adding process and tag restoring process are executed by using pipeline registers, a queue memory and simple control circuit, thereby obtaining high speed operation and superior throughput without the need for a tag memory table, complicated operation-test circuitry or a sequence control circuit.

Tag Data processing apparatus for a data flow computer

In a data transmission apparatus, a plurality of data processing modules are used and required sequence setting is performed to a port sequencer of input/output ports of each data processing module. The daisy chain transfer of the selective data transfer, the load distribution data transfer, the collective data transfer is combined between the data processing modules, thereby the data transmission is performed efficiently at high speed.

Cascaded information processing module having operation unit, parallel

A coincidence element responsive to a plurality of input signals for outputting the level of the input signals when said plurality of input signals coincide with each other includes, a serial connection of a first electrically conductive type and a second electrically conductive type MOS transistors of the same number, the number being equal to the number of the input signals, responsive to said plurality of inputs connected between a first power supply and a second power supply; and a CMOS inverter responsive to an intermediate output at the connection of the most lower stage first conductivity type MOS transistor and the most upper stage second conductivity type MOS transistor for outputting a coincidence signal.

Coincidence element and a data transmission path

A simulation method and a computer therefor, i.e., a simulator, for simulating operation of a circuit employing logic gates. The simulation method is to be called the event drive method, in which the output processing is executed only when an input to cause output changes and the output level and the start and finish time for the level are sent out. Hence the number of packets of data flowing for simulation can be minimized and also the number of times of data processing is reduced. This system is applied to each component in a logic circuit, whereby the parallel execution of processing as to the parallel components is possible so as to devise the simulation at a higher speed.

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Osaka, Japan

Hajime Asano