Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

Japan Atomic Energy Research Institute

Jfe Engineering Corporation

Hajime Akiyama

Akira Okada

Kinya Yamashita

Kazuhiro Shimizu

Naoki Yasuda

Takaya Noguchi

Norihiro Takesako

Kazunari Hatade

Shinichi Izuo

Hisao Kondoh

Takashi Nakayama

Yoichiro Tarui

Manabu Yoshino

Takeshi Uchiyama

Junya Watanabe

Keiichi Okuyama

Kazumasa Wakimoto

Yousuke Morita

Masahito Yoshikawa

Takeshi Ohshima

Kenichi Honda

Akio Shimomura

Satoshi Horiuchi

The object of the present invention is to increase the breakdown voltage without thickening an SOI layer in a wafer-bonded dielectric isolated structure. A device region of a SiC-SOI device includes: a first trench continuously or intermittently surrounding an ntype drift region and not penetrating a SiC substrate; an ntype side surface diffusion region formed on each side surface of the first trench; an ntype bottom diffusion region formed under the ntype drift region and in contact with the ntype side surface diffusion region; and a plurality of thin insulating films formed in proximity to a surface of the ntype drift region at regular spacings of 0.4 &#x3bc;m or less. A surrounding region includes a second trench formed to continuously surround the first trench and penetrating the SiC substrate, and an isolated insulating film region formed on each side surface of the second trench.

SiC-SOI device and manufacturing method thereof

A purpose of the present invention is to provide a technique capable of suppressing an electric discharge during evaluation. A semiconductor device includes: a semiconductor base body having an element region and a terminal region; a plurality of electrode pads disposed in an area that is in the element region of the semiconductor base body and is separated from the terminal region, an insulating protection film having an opening provided above each of the electrode pads; and a plurality of conductive layers disposed on the protection film and electrically connected to the plurality of electrode pads, respectively, through the opening. In a planar view, each of the conductive layers is extended to the terminal region or the vicinity of the terminal region.

Semiconductor device and method for testing same

Problem to be Solved To provide a waste gasification melting apparatus which, even if a fuel gas is used as an alternative to a part of the coke, the temperature of the coke bed can be sufficiently raised, and a method using the same. Solution A waste gasification melting apparatus including an oxygen rich air supply apparatusfor blowing oxygen rich air into a tuyere, and a fuel gas supply apparatusfor supplying a fuel gas to the tuyere, and a controllerfor controlling the oxygen rich air supply apparatus; the oxygen rich air supply apparatusmixing air and oxygen to prepare oxygen rich air and supply the oxygen rich air to the tuyere; and the controllercontrolling the amount of air to be mixed and the amount of oxygen to be mixed in the oxygen rich air supply apparatusso as to give an oxygen concentration of the oxygen rich air in accordance with the amount of fuel gas supplied to the tuyerefrom the fuel gas supply apparatus

Waste gasification melting apparatus and waste gasification melting method using the same

A purpose of the present invention is to provide a semiconductor device that can restrain occurrence of partial discharge in evaluation of electric characteristics and can carry out failure analysis from the upper side of a measurement object. A semiconductor device according to the present invention includes: at least one electrode; a protective layer having at least one opening part provided such that a portion of the electrode is exposed at the opening part, and being formed to cover the other portion of the electrode excluding the portion of the electrode exposed at the opening part, the protective layer being insulative; and a conductive layer formed so as to cover the protective layer and the opening part and be directly connected to the electrode at the opening part.

Semiconductor device and electrical contact structure thereof

An apparatus for evaluating a semiconductor device includes: a chuck stage for fixing a semiconductor device; an insulating substrate; a plurality of probes fixed to the insulating substrate; a temperature adjustment unit adjusting temperatures of the plurality of probes; an evaluation/control unit causing a current to flow into the semiconductor device through the plurality of probes to evaluate an electric characteristic of the semiconductor device; an inspection plate having a front surface and a rear surface opposite to each other; a thermal image measurement unit acquiring a thermal image of the inspection plate when distal end portions of the plurality of probes are pressed against the front surface; and a thermal image processing unit performing image processing to the thermal image to obtain in-plane positions and temperatures of the distal end portions of the plurality of probes.

Apparatus and method for evaluating semiconductor device comprising thermal image processing

An apparatus for evaluating a semiconductor device includes: a chuck stage; an insulating substrate; a plurality of probes; a temperature adjustment unit; an evaluation/control unit; and a probe position/temperature inspection device including an inspection plate, a thermo-chromic material, a photographing unit, and an image processing unit. The photographing unit photographs a color-change image of the thermo-chromic material in a state in which distal end portions of the plurality of probes are pressed against the upper surface of the inspection plate. The image processing unit performs image processing to the color-change image to calculate in-plane positions and temperatures of the distal end portions of the plurality of probes.

Apparatus and method for evaluating semiconductor device

A semiconductor device inspection apparatus includes probe sockets and an insulating plate that holds probes via the probe sockets. The probe sockets each include an opposing part that opposes the insulating plate in the direction in which the probe is pressed and has a pressure passive member disposed in the opposing part. The insulating plate is transparent. When pressing force is applied to the tips of the probes, the pressure passive members are pressed between the opposing parts of the probe sockets and the insulating plate. The semiconductor device inspection apparatus further includes a camera to capture an image of the pressure passive members from the opposite side of the insulating plate to the side on which the pressure passive members are disposed, and an image processor to process the image captured by the camera to detect the presence or absence of pressure received by the pressure passive members.

Semiconductor device inspection apparatus and semiconductor device inspection method

A semiconductor evaluation apparatus includes a jig for evaluation and a probe substrate. The jig for evaluation is provided such that a plurality of semiconductor devices can be placed thereon. The probe substrate is provided so as to face the jig for evaluation, and includes a contact probe. The jig for evaluation includes a plurality of housing portions divided by a frame portion such that the plurality of semiconductor devices can be separately placed on the plurality of housing portions, respectively. The semiconductor evaluation apparatus is configured such that the contact probe can be brought into contact with a plurality of elements in the state where a space is provided by bringing the frame portion and the probe substrate in proximity to each other. In this space, each of the plurality of semiconductor devices is placed between a corresponding one of the plurality of housing portions and the probe substrate.

Semiconductor evaluation apparatus

A device includes a jig having a plate with through-holes formed therein and also having a frame formed on the plate so as to be able to accommodate a plurality of semiconductor chips in spaced relationship, a foreign matter capture member having a first charge section with a first flat surface and a second charge section with a second flat surface, the second charge section being insulated from the first charge section, charging means for positively charging the first flat surface and negatively charging the second flat surface, and sliding means for causing either the jig or the foreign matter capture member to slide relative to the other in such a manner that the through-holes of the jig are spaced a predetermined distance from the first and second flat surfaces. The through-holes are formed in different regions defined and surrounded by the frame.

Foreign matter removal device and foreign matter removal method

A semiconductor device assessment apparatus that electrically assesses a semiconductor device formed on a semiconductor substrate includes a holding unit having a surface to hold the semiconductor substrate thereon, and a detection unit to detect irregularity on the surface of the holding unit. The holding unit on the surface includes a plurality of grooves formed such that when the semiconductor substrate is held on the surface, the grooves overlap a periphery of the semiconductor substrate and also have a portion located outer than the periphery of the semiconductor substrate.

Semiconductor device assessment apparatus

A semiconductor testing jig fixes a measurement target while it is held between a chuck stage and the measurement target. The semiconductor testing jig includes a base on which the measurement target is to be installed and which can be attached to the chuck stage. The base includes: a first main surface to become an installation surface for the measurement target; a second main surface opposite the first main surface and which is to contact the chuck stage; and a porous region containing a porous member. The porous region is provided selectively as seen in plan view, and penetrates through the base from the first main surface toward the second main surface.

Semiconductor testing jig and semiconductor testing method performed by using the same

A semiconductor evaluating device includes a chuck stage for holding a semiconductor device serving as a measuring object, a contact probe for evaluating an electrical characteristic of the semiconductor device by getting contact with the semiconductor device held on the chuck stage, and a fluid spraying portion for spraying a fluid onto the semiconductor device.

Semiconductor evaluating device and semiconductor evaluating method

A method of attaching a wafer by suction, includes a step of mounting a wafer on a right arm and a left arm of a transfer jig, moving the transfer jig toward a wafer suction stage in such a manner that a facing right arm surface of the right arm slides along and in contact with a first side surface of the wafer suction stage and a facing left arm surface of the left arm slides along and in contact with a second side surface of the wafer suction stage until the wafer comes to lie directly above a mounting surface of the wafer suction stage, mounting the wafer on the mounting surface by moving the transfer jig downward toward the wafer suction stage while maintaining the contacts, and attaching the wafer to the mounting surface by suction.

Wafer suction method, wafer suction stage, and wafer suction system

A semiconductor testing jig is provided with a conductive stage including a plurality of mounting portions on which a plurality of vertical semiconductor devices are each individually disposed with lower surface electrodes being in contact with the plurality of mounting portions, an insulating frame portion having a lattice pattern that is disposed on the stage and surrounds each of the plurality of mounting portions in plan view to define each of the mounting portions, and an abrasive layer disposed in a position in the frame portion, the position facing each of the vertical semiconductor devices disposed on the mounting portions.

Semiconductor testing jig and transfer jig for the same

An inspection apparatus includes an insulating substrate, a socket in which a body portion having a through-hole in a wall thereof is integrally formed with a connection portion secured to the insulating substrate, and a contact probe detachably secured to the socket.

Growing community of inventors

Tokyo, Japan

Hajime Akiyama