Altera Corporation

Legend Silicon Corporation

Haiyun Yang

Martin Langhammer

Peng T Li

Divya Vijayaraghavan

Herman Henry Schmit

David Wolk Mendel

Keith Duwel

Ninh D Ngo

Huy X Ngo

Tianshu Chi

One embodiment relates a method of receiving data from a multi-lane data link. The data is encoded with an FEC code having a block length. The data is FEC encoded at a bus width which is specified within particular constraints. One constraint is that the FEC encoder bus width in bits is an exact multiple of a number of bits per symbol in the data. Another constraint may be that the FEC code block length is an exact multiple of the FEC encoder bus width. Another constraint may be that the FEC encoder bus width is an exact multiple of a number of serial lanes of the multi-lane interface. Other embodiments and features are also disclosed.

Circuit structure and method for high-speed forward error correction

Integrated circuits with pseudo random bit sequence (PRBS) generation circuitry are provided. The PRBS generation circuitry may be configured to support parallel output generation in multiple modes, where the parallel bit width in each mode can be different. The PRBS generation circuitry may include a linear feedback shift register that implements a desired polynomial, one or more XOR tree circuits that produces the parallel output bits, a multiplexer for selectively routing a subset of the parallel output bits back to the input of the shift register, and a gearbox for performing an adjustable bit width conversion. Configured in this way, the PRBS generation circuitry can provide parallel PRBS generation with an adjustable bit width.

Parallel pseudo random bit sequence generation with adjustable width

One embodiment relates a method of receiving data from a multi-lane data link. The data is encoded with an FEC code having a block length. The data is FEC decoded at a bus width which is specified within particular constraints. One constraint is that the FEC decoder bus width in bits is an exact multiple of a number of bits per symbol in the data. Another constraint may be that the FEC code block length is an exact multiple of the FEC decoder bus width. Another constraint may be that the FEC decoder bus width is an exact multiple of a number of serial lanes of the multi-lane interface. Other embodiments and features are also disclosed.

Systems and methods and systems are disclosed for allowing the medium access control (MAC) layer in a communication system within an integrated circuit or device to accurately determine a timestamp point and a timestamp value when, for example, the Precision Time Protocol (PTP) protocol is in use by the communication system. Such determination of accurate timestamp point and timestamp value may be used by the communication system to account for and to compensate for the time shift(s) from forward error correction (FEC) sublayer changes in a data frame that is transmitted by the MAC layer. Feedback is provided to the MAC from the FEC to allow the MAC to accurately determine the timestamp point and timestamp value align preamble of the data frame to the beginning of the FEC bit block that is output by the FEC sublayer.

Methods to achieve accurate time stamp in IEEE 1588 for system with FEC encoder

Systems, methods, apparatus, and techniques relating to a transmitter interface are disclosed. A soft-IP transmitter interface includes a Reed-Solomon encoder operating according to any one of multiple bus width and bandwidth parameter pairs, and a gearbox module that includes multiple gearboxes. The multiple gearboxes receive input data at a bus width and clock rate parameter pair specified by the soft-IP transmitter interface and convert the input data into output data according to a number of physical lanes and bandwidth parameter pair specified by a physical medium attachment (PMA) standard.

Flexible high speed forward error correction (FEC) physical medium attachment (PMA) and physical coding sublayer (PCS) connection system

One embodiment relates to a frame detection circuit for detecting a frame boundary. The circuit includes at least two frame buffers and a staged-parallel structure of syndrome computation circuits that computes a number of syndromes in one cycle. The two frame buffers are each one word in width. The number of syndromes computed in one cycle by the cascaded series is a fraction of a number of bits in one word. Another embodiment relates to a method for detecting a frame boundary. Another embodiment relates to a method for computing a current syndrome. Other embodiments, aspects, and features are also disclosed.

Methods and apparatus for frame detection

Method and system for determining the number of one or more of a sequence of M+1 consecutive OFDM frames from analysis of the designated preambles of two or more consecutive frames (m=0, 1, . . . , M; M&#x2267;1). An overlap function OF(m;k) is formed for each frame with a sequence of selected reference signals indexed by k (k=1, 2, . . . , K), dependent upon the frame number m and the index k, and a phase (sequence location corresponding to largest amplitude of overlap function) is determined. An Mth-order phase difference is computed that corresponds to frame number of one of the M+1 frames. A consistency check is provided for the phase numbers.

Growing community of inventors

San Jose, CA, United States of America

Haiyun Yang