Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Ca, Inc.

Semiconductor Manufacturing (beijing) International Corporation

Semiconductor Manufacturing (shanghai) International Corporation

Semiconductor Manufacturing International Corp.

China Unionpay Co., Ltd.

Semiconductor Manufacturing (shanghai) Corporation

Haiyang Zhang

Chenglong Zhang

Shaorong Li

Xiaopin Wang

Guoxian Shang

Shiliang Ji

Bo Su

Zhuofan Chen

Panpan Liu

Xinpeng Wang

Dongjiang Wang

Junqing Zhou

Yan Wang

Erhu Zheng

Jun Yang

Qiuhua Han

Xiaoying Meng

Qingtian Ma

Shishen Liu

Lei Huang

Xuan Zhang

Ran Shuai

Guodong Li

Victor Liu

Minda Hu

Xiaopin (Hector) Wang

Zhenyang Zhao

Lei Wang

Pengfei Yu

Wei Zhang

Fan Li

Yiying Zhang

Hector Wang

Fei Zhang

Sen Yang

Xiaoming Zhang

Wei Tian

Alexey Shvechkov

Jinxing Yin

Jiaolin Yang

Gongjun Fei

Jia Ren

Gong Jun Fei

Rongyao Chang

Ermin Chong

Yibin Song

Longjuan Tang

Raymond Huang

Shisheng (Victor) Liu

Fangyuan Xiao

Shuaijie Chi

Enning Zhang

Chenxi Yang

Semiconductor structures and forming methods are disclosed. One form of a method includes: forming mask spacers on a base; patterning a target layer using the mask spacers as masks, to form discrete initial pattern layers, where the initial pattern layers extend along a lateral direction and grooves are formed between a longitudinal adjacent initial pattern layers; forming boundary defining grooves that penetrate through the initial pattern layers located at boundary positions of the target areas and cutting areas along the lateral direction; forming spacing layers filled into the grooves and the boundary defining grooves; and using the spacing layers located in boundary defining grooves and the spacing layers located in the grooves as stop layers along the lateral and the longitudinal directions respectively, etching the initial pattern layers located in the cutting areas, and using the remaining initial pattern layers located in the target areas as the target pattern layers.

Semiconductor structure and forming method thereof

Semiconductor structure and method of forming semiconductor structure are provided. The semiconductor structure includes a substrate, a first isolation structure, and a first nanostructure and a second nanostructure on two sides of the first isolation structure. The semiconductor structure also includes a second isolation structure, and a third nanostructure and a fourth nanostructure on two sides of the second isolation structure. A top of the second isolation structure is lower than a top of the first isolation structure. The semiconductor structure also includes a first gate structure and a second gate structure. The first gate structure and the second gate structure expose a top surface of the first isolation structure. The semiconductor structure also includes a third gate structure and a fourth gate structure. The third gate structure and the fourth gate structure are in contact with each other on a top surface of the second isolation structure.

Semiconductor structure and method of forming semiconductor structure

Semiconductor structures and fabrication methods thereof are provided. The method may include providing a to-be-etched layer; forming a plurality of core layers on the to-be-etched layer, wherein a first opening and a second opening are formed between different adjacent core layers and a width of the first opening is smaller than a width of the second opening; forming a first sacrificial material layer on the to-be-etched layer and the plurality of core layers; forming a second sacrificial layer on a portion of the first sacrificial material layer in the first opening to form a sacrificial structure in the first opening; removing the plurality of core layers after forming the sacrificial structure; forming sidewall spacers on sidewall surfaces of the sacrificial structure after removing the plurality of core layers; and removing the sacrificial structure after forming the sidewall spacers.

Semiconductor fabrication method and structure using multiple sacrificial layers to form sidewall spacers

The present disclosure provides a method and a device for transaction clearing. The method includes receiving first clearing requests transmitted by a quantity N of terminals, where N>1; according to the first clearing requests, acquiring transaction data of the quantity N of terminals from a database; initializing a cache queue, and loading the transaction data into the cache queue; reading the transaction data in the cache queue, and performing a clearing process on the transaction data; and writing a clearing result into the database and feeding back the terminals with an execution result of the first clearing requests.

Transaction settlement method and apparatus

Semiconductor structure and fabrication method are provided. The semiconductor structure includes a substrate, including a first region and a second region; a plurality of fins, formed on the first region of the substrate; a first isolation structure, formed on the first region between adjacent fins and on the second region of the substrate; a second isolation structure, formed in each fin and in the first isolation structure, over the first region of the substrate; and a power rail, formed in the isolation structure and partially in the substrate of the second region.

Semiconductor structure and method for fabricating the same

The present disclosure provides a method for forming a semiconductor structure. The method includes providing a target etching layer; sequentially forming an initial mask layer, an anti-reflection layer, and a patterned structure on the target etching layer; performing a first etching process on the anti-reflection layer to remove a surface portion of the anti-reflection layer using the patterned structure as a mask; performing a surface treatment process on the patterned structure; and performing a second etching process on the anti-reflection layer until exposing a surface of the initial mask layer.

Semiconductor structure and fabrication method thereof

The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, having a plurality of fins on a surface of the substrate; a gate structure across the plurality of fins. The gate structure is located on a portion of a top surface and sidewall surfaces of the plurality of fins. The gate structure includes a first region and a second region on the first region. A bottom boundary of the second region is higher than the top surface of the plurality of fins. A size of the first region in an extending direction of the plurality of fins is smaller than a size of the second region in the extending direction of the plurality of fins.

Semiconductor device

Semiconductor device fabrication method is provided. The method includes providing a substrate; forming a first semiconductor layer on the substrate; forming a stack of semiconductor layer structures on the first semiconductor layer, each of the semiconductor layer structures comprising a second semiconductor layer and a third semiconductor layer on the second semiconductor layer, the second and third semiconductor layers having at least a common compound element, and the third semiconductor layer and the first semiconductor layer having a same semiconductor compound; performing an etching process to form a fin structure; performing a selective etching process on the second semiconductor layer to form a first air gap between the first semiconductor layer and the third semiconductor layer and a second air gap between each of adjacent third semiconductor layers in the stack of one or more semiconductor layer structures; and filling the first and second air gaps with an insulator layer.

Semiconductor device fabrication method

Semiconductor structures and fabrication methods thereof are provided. The method includes providing a substrate; forming a stacked material structure on the substrate; and forming trenches in the stacked material structure. Bottoms of the trenches are in the first material layer, the trenches are arranged along a first direction and form an initial stacked structure sequentially including an initial first layer, an initial second layer and an initial third layer. The method also includes etching the initial third layer to form transitional third layers arranged along a second direction perpendicular to the first direction; removing a portion of the initial first layer and a portion of the initial second layer of the initial stacked structure at two sides along the second direction to form a stacked structure including a first layer, a second layer and the transitional third layers; and forming a gate structure.

Semiconductor structures and fabrication methods thereof are provided. The semiconductor includes a substrate; a gate structure on the substrate; and a dielectric layer on the substrate and covering sidewall surfaces of the gate structure. The dielectric layer includes an opening passing through the gate structure along a direction perpendicular to an extending direction of the gate structure. The semiconductor structure also includes a first isolation layer in the opening and with a top surface lower than a top surface of the gate structure.

A semiconductor structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of fins on the substrate, and forming an isolation structure layer including a plurality of isolation structures on the substrate, each isolation structure being formed between adjacent fins. The method further includes forming a first opening by etching at least one isolation structure of the plurality of isolation structures and a portion of the substrate, and forming a power rail by filling the first opening with a conductive material, where a top surface of the power rail is lower than a top surface of the plurality of fins.

A method for forming a semiconductor structure includes providing a substrate; forming a gate structure on the substrate, the gate structure extending along a first direction; removing a portion of the gate structure to form a trench in the gate structure, the trench penetrating through the gate structure along a second direction which is different form the first direction; performing a first cleaning treatment process on the trench to remove non-metal residues; and performing a second cleaning treatment process on the trench to remove metal residues.

Semiconductor structure and method for forming the same

The present disclosure provides a method for forming a semiconductor structure. The method includes providing a to-be-etched layer; forming a plurality of initial sidewall spacers on the to-be-etched layer; and performing at least one modification treatment process on the plurality of initial sidewall spacers to form a plurality of sidewall spacers. Each of the at least one modification treatment process includes modifying the plurality of initial sidewall spacers to form a transition layer on the top and sidewall surfaces of each initial sidewall spacer of the plurality of initial sidewall spacers, and then removing the transition layer.

Semiconductor structure and fabrication method are provided. The method includes providing a substrate including a first region and a second region; forming a plurality of fins on the first region of the substrate; forming an isolation structure on the first region and the second region of the substrate; forming a gate structure across the plurality of fins and on the isolation structure at the first region; etching the isolation structure and the substrate at the second region to form a first opening; filling the first opening with a conductive material layer; and etching the gate structure till exposing the isolation structure to form a second opening in the gate structure and removing a portion of the conductive material layer in the first opening to form a power rail.

Growing community of inventors

Shanghai, China

Haiyang Zhang