Southeast University

Haiyang Jiang

Peng Cao

Jiahao Wang

Qianqian Song

Bingqian Xu

Disclosed is a near-threshold cell circuit delay model, where obtaining parameters includes obtaining process parameters, current parameters and delay parameters with slow input transition; judging a cell circuit type includes judging whether a cell circuit is an inverter, a stacked structure cell or a parallel structure cell, calculating currents and a current integral according to the cell circuit type, calculating a mean value, a variance and a skewness of a logarithm of the current sum, and calculating a mean value and a variance of an equivalent threshold voltage; judging a delay type includes calculating an overshoot time and a delay according to the cell circuit type, comparing the magnitude relationship among an input transition time, the overshoot time and the delay, and judging whether the delay type is ultra-fast input, fast input or slow input; establishing a cell circuit nominal delay model is establishing the cell circuit nominal delay model according to the cell circuit type and the delay type, and obtaining a nominal delay value; and establishing a cell circuit statistical delay model is establishing the cell circuit statistical delay model according to the cell circuit type and the delay type.

Near-threshold cell circuit delay model

Disclosed in the present invention is a method for optimizing circuit timing based on a flexible register timing library. First, registers are simulated respectively in a case of a plurality of groups of an input signal conversion time, a clock signal conversion time, and a register load capacitance, corresponding actual propagation delays at this time are obtained by changing setup slack and hold slack of the registers, and actual propagation delays of the registers under specific input signal conversion time, clock signal conversion time, register load capacitances, setup slack, and hold slack are obtained through linear interpolation, to establish a flexible register timing library; and then static timing analysis is performed on all register paths in a circuit by using the library, a minimum clock cycle under a condition of satisfying that a setup time margin and a hold time margin are both greater than zero is found by changing the setup slack and hold slack of the registers, thereby improving the performance of the circuit without changing the design of the circuit and without increasing the area overheads of the circuit.

Method for optimizing circuit timing based on flexible register timing library

Disclosed in the present invention is a flexible modeling method for a timing constraint of a register. Simulation ranges of input terminal transition time, clock terminal transition time, and output load capacitance of a register are determined first, simulation is performed under each combination of input terminal transition time, clock terminal transition time, and output load capacitance to obtain a timing constraint range, then setup slack and hold slack are extracted in this constraint range with a particular interval, and then simulation is performed to obtain a clock terminal-to-output terminal delay. Finally, a mutually independent timing model of the register is established by using an artificial neural network, where the clock terminal-to-output terminal delay is modeled as a function of the input terminal transition time, the clock terminal transition time, the output load capacitance, the setup slack, the hold slack, and an output terminal state. A flexible timing constraint model in the present invention has advantages of low simulation overheads and high prediction precision, and is of great significance for static timing analysis timing signoff of a digital integrated circuit.

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Jiangsu, China

Haiyang Jiang