Inspur Suzhou Intelligent Technology Co., Ltd

Haiwei Liu

Yaqian Zhao

Gang Dong

Hongbin Yang

Rengang Li

Lingyan Liang

Dongdong Jiang

Wenfeng Yin

Qichun Cao

A neural network compression method whereby forward inference is performed on target data by using a target parameter sharing network to obtain an output feature map of the last convolutional module, a channel related feature is extracted from the output feature map, the extracted channel related feature and a target constraint condition are input into a target meta-generative network, and an optimal network architecture under the target constraint condition is predicted by using the target meta-generative network to obtain a compressed neural network model.

Neural network compression method, apparatus and device, and storage medium

An image recognition method and apparatus based on a systolic array, and a medium are disclosed. The method includes: converting obtained image feature information into a one-dimensional feature vector; converting an obtained weight matrix into a one-dimensional weight vector, and allocating a corresponding weight group to each node in a trained three-dimensional systolic array model; performing multiply-accumulate of the feature vector and a weight value on the one-dimensional feature vector in parallel by using the three-dimensional systolic array model, to obtain a feature value corresponding to each node, the feature values with different values reflecting article categories contained in an image; and determining an article category contained in the image according to the feature value corresponding to each node and a pre-established corresponding relationship between the feature value and the article category.

Image recognition method and apparatus based on systolic array, and medium

A system for accelerating an RNN network including: a first cache, which is used for outputting Wto Wor Wto Win parallel in N paths in a cyclic switching manner, and the degree of parallelism is k; a second cache, which is used for outputting xor hin the cyclic switching manner; a vector multiplication circuit, which is used for, by using N groups of multiplication arrays, respectively calculating Wxto Wx, or respectively calculating Whto Wh; an addition circuit, which is used for calculating Wx+Wh+bto Wx+Wh+b; an activation circuit, which is used for performing an activation operation according to an output of the addition circuit; a state updating circuit, which is used for acquiring c, calculating cand h, updating c, and sending hto the second cache; a bias data cache; a vector cache; and a cell state cache.

System and method for accelerating RNN network, and storage medium

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Jiangsu, China

Haiwei Liu