Lsi Corporation

Avago Technologies General IP (singapore) Pte. Ltd.

Link a Media Devices Corporation

Seagate Technology Incorporated

Avago Technologies International Sales Pte. Limited

Haitao Xia

Shaohua Yang

Fan Zhang

Ming Jin

Lu Lu

Haotian Zhang

Jun Xiao

Lu Pan, Sr

Dahua Qin

Jianzhong Huang

Yu Liao

Xun Zhang

Shu Li

Rui Cao

Wu Chang

Bruce Alexander Wilson

Nayak Ratnakar Aravind

George Mathew

Mohammad Shafiul Mobin

Weijun Tan

Scott M Dziak

Yenyu Hsieh

Seongwook Jeong

Marcus Marrow

Shih-Ming Shih

Johnson Yen

Lei Chen

Xuebin Wu

Kai Keung Chan

Ryan Yu

Yu Kou

Nenad Miladinovic

Richard Rauschmayer

Zhi Bin Li

Bac V Pham

Parviz Rahgozar

Kenneth M Hall

Mark A Landreth

Hongwei Song

Zongwang Li

Yang Han

Chung-Li Wang

Xiufeng Song

Victor A Krachkovsky

Anup S Tirumala

Jin Lu

Lingyan Sun

Yuqing Yang

John Jansen

Xiao Yuan Ma

Fuminori Sai

Mark D Thornley

Aravind Ratnakar Nayak

Ku Hong Jeong

William J Ledden

Lu Pan

The present inventions are related to systems and methods for accessing data from a flash memory, and more particularly to systems and methods for inter-cell interference handling in a flash memory. The systems and methods may include a soft information correction circuit that is operable to receive soft information corresponding to information accessed from a block of memory cells, and modify the soft information based upon a variance of the soft information and a median of the soft information to create corrected soft information, the corrected soft information being used to mitigate inter-cell interference in the block of memory cells.

Systems and methods for inter-cell interference mitigation in a flash memory

Embodiments are related to systems and methods for data transfer, and more particularly to systems and methods for providing non-standard bus information.

Systems and methods for channel information exchange in a PCIe environment

Embodiments are related to systems and methods for data transfer, and more particularly to systems and methods for providing transfer margin information.

Systems and methods for accurate transfer margin communication

Systems and method relating generally to data processing, and more particularly to systems and methods for accessing a data set from a solid state storage device, using a data decoding circuit to apply a data decoding algorithm to the data set to yield a decoded output, where the decoded output includes at least one error, identifying at least one critical location in the data set, and estimating a voltage associated with the data in the data set corresponding to the critical location.

Systems and methods for enhanced data recovery in a solid state memory system

An apparatus for processing data includes a decision feedback equalizer configured to sample an analog signal to yield digital data and a DC offset adaptation circuit. The decision feedback equalizer is configured to sample the equalized signal using at least one data latch at a first data latch threshold value and at a second data latch threshold value. The DC off set adaptation circuit is configured to calculate a DC off set in the analog signal based on the first data latch threshold value and on the second data latch threshold value.

DeSerializer DC offset adaptation based on decision feedback equalizer adaptation

An apparatus for processing data includes a linear equalizer, a load switchably connected to an output of the linear equalizer, a slicer configured to sample a signal derived from the output of the linear equalizer, and a detector circuit configured to detect an over-equalization condition in data to be sampled by the slicer and to connect the load to the output of the linear equalizer in the over-equalization condition.

Receiver bandwidth adaptation

Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for enhancing margin in a serial data transfer.

Systems and methods for serial data transfer margin increase

Systems and methods are disclosed relating generally to data processing, and more particularly to applying low pass and rotation filtering in relation to data processing. For example, a system may include a phase modification value determination circuit operable to generate a phase offset value based upon an input data set derived from information sensed from a storage medium. The system may include an integrated low pass and rotation filtering circuit operable to simultaneously apply a low pass filtering function and phase rotation function to a series of digital samples derived from the information sensed from the storage medium to yield a modified output. Application of both the low pass filtering and phase rotation functions is governed at least in part based upon a selected coefficient set corresponding to a combination of the phase off set value and a boost value.

Systems and methods for a data processing using integrated filter circuit

An apparatus for controlling a feedback loop includes a digital finite impulse response filter configured to equalize digital samples to yield equalized data, a data detector circuit configured to detect values of the equalized data to yield detected data, a pattern detection circuit configured to detect at least one pattern in the detected data, an expected value comparison circuit configured to compare the digital samples corresponding to the at least one pattern with an expected value, and a feedback loop adaptation circuit configured to control a feedback loop based in part on whether the at least one pattern is detected by the pattern detection circuit and on an output of the expected value comparison circuit.

Loop adaptation control with pattern detection

Systems and method are disclosed relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device. One example of the system includes a first equalizer circuit, a second equalizer circuit, a summation circuit, a first multiplication circuit, a second multiplication circuit, and a scalar calculation circuit that is capable of calculating a scalar based upon coefficients that are also provided as inputs to the first equalizer and second equalizer.

Systems and methods for multi-head coefficient based scaling

Systems and methods relating generally to data processing, and more particularly to adjusting gain parameters in relation to data processing.

Systems and methods for acquisition phase gain modification

A method for calculating an average phase offset in a two dimensional magnetic recording system includes calculating a phase offset as a difference between a phase of a first signal derived from a first read head and a second phase of a second signal derived from a second read head, correcting for phase wrapping differences between the phase offset and a previous phase offset, determining whether the phase offset is consistent with the previous phase offset, and calculating an average phase offset which includes the phase offset only if it is consistent with the previous phase offset.

Two dimensional magnetic recording head separation calculator

Systems and method relating generally to data processing, and more particularly to systems and methods for fragmenting a data set and recovering the fragmented data set. As one example, a data processing system is discussed that includes: a fragmenting circuit operable to separate a data set into at least a first fragment and a second fragment; and a transfer packet formation circuit operable to: append identification information to the front of the first fragment, and at least a first M+N bits of the second fragment to the end of the first fragment to yield a first transfer fragment, and aggregate the first transfer fragment with other transfer fragments to yield an aggregate output.

Systems and methods for fragmented data recovery

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San Jose, CA, United States of America

Haitao Xia