Micron Technology Incorporated

Intel Corporation

Lodestar Licensing Group LLC

Haitao Liu

Kamal M Karda

Durai Vishak Nirmal Ramaswamy

Akira Goda

Chandra V Mouli

Sanh D Tang

Guangyu Huang

Deepak Chandra Pandey

Karthik Sarpatwari

Litao Yang

Albert Fayrushin

Srinivas Pulugurtha

Krishna Kumar Parat

Yunfei Gao

Si-Woo Lee

Scott E Sills

Kirk D Prall

Justin B Dorhout

Jian Li

Gurtej S Sandhu

Richard J Hill

Han Zhao

Ramanathan Gandhi

Fatma Arzum Simsek-Ege

Richard Edward Fackenthal

Ashonita A Chavan

Qian Tao

Vladimir Mikhalev

Wolfgang Mueller

Toru Tanzawa

Koji Sakui

Lifang Xu

Shigekazu Yamada

Sourabh Dhir

Naveen Kaushik

John K Zahurak

Augusto Benvenuti

Changhyun Lee

Aurelio Giancarlo Mauri

Mojtaba Asadirad

John A Smythe

Michael A Smith

Duane R Mills

Jie Sun

Zhenyu Lu

Eric S Carman

Yi Fang Lee

Sergei V Koveshnikov

Srikant Jayanti

Dimitrios Pavlopoulos

Luan C Tran

Seiichi Aritome

Martin Ceredig Roberts

Paolo Tessariol

Indra V Chary

Lars P Heineck

Robert B Kerr

Sangmin Hwang

Fawad Ahmed

Di Li

Sameer Chhajed

Luca Laurin

Kunal R Parekh

Yongjun Jeff Hu

Nishant Sinha

Hong Li

Roger W Lindsay

Tomoko Ogura Iwasaki

Yoshihiko Kamata

Matthew J King

Andrew Bicksler

Shu Qin

Alessandro Calderoni

Rajesh N Gupta

Christian Caillat

Sidhartha Gupta

Nicholas R Tapias

Pankaj Sharma

Kyle A Ritter

Benben Li

Siddartha Kondoju

Tomoharu Tanaka

Yingda Dong

Michael P Violette

Mark Alan Helm

Mark Fischer

Chris M Carlson

Kenneth William Marr

Stephen J Kramer

Collin Howder

David K Hwang

Sumeet C Pandey

Makoto Morino

Yijie Zhao

Fredrick David Fishburn

Soichi Sugiura

Mingtao Li

Ankit Sharma

Some embodiments include apparatuses and methods of using the apparatuses. One of the apparatuses includes first, second, and third conductive structures, each having a length in a first direction, first and second memory cells spaced apart from each other in a second direction perpendicular to the first direction, first conductive regions, and second conductive regions. Each of the first and second memory cells includes a first semiconductor portion located on a first level of the apparatus and coupled to the third conductive structure and one of the first and second conductive structures, a second semiconductor portion located on a second level of the apparatus and coupled to one of the first and second conductive structures. The first conductive regions are opposite the first and second semiconductor portions, respectively, of the first memory cell. Second conductive regions are opposite the first and second semiconductor portions, respectively, of the second memory cell.

Memory device having tiers of 2-transistor memory cells

Some embodiments include a ferroelectric transistor having a first electrode and a second electrode. The second electrode is offset from the first electrode by an active region. A transistor gate is along a portion of the active region. The active region includes a first source/drain region adjacent the first electrode, a second source/drain region adjacent the second electrode, and a body region between the first and second source/drain regions. The body region includes a gated channel region adjacent the transistor gate. The active region includes at least one barrier between the second electrode and the gated channel region which is permeable to electrons but not to holes. Ferroelectric material is between the transistor gate and the gated channel region.

Ferroelectric transistors and assemblies comprising ferroelectric transistors

A memory device includes an array of memory cells and a plurality of bit-lines with each bit-line connected to a respective set of memory cells of the array of memory cells. The memory device includes a memory subsystem having first and second memory circuits. Each first memory circuit can be disposed laterally adjacent to a second memory circuit. Each first memory circuit includes a first bit-line connection and each second memory circuit including a second bit-line connection, the first and second bit-line connections can connect to respective bit-lines. Each first bit-line connection is disposed on a first bit-line connection line of the memory subsystem and each second bit-line connection is disposed on a second bit-line connection line of the memory subsystem, and the second bit-line connection line can be offset from the first bit-line connection line by a predetermined distance that is greater than zero.

Reduced pitch memory subsystem for memory device

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line, a second data line, a conductive line, and a memory cell coupled to the first and second data lines. The memory cell includes a first transistor and a second transistor. The first transistor includes a first region electrically coupled to the first and second data lines, and charge storage structure electrically separated from the first region. The second transistor includes a second region electrically separated from the first region, the second region electrically coupled to the charge storage structure and the second data line. The conductive line is electrically separated from the first and second channel regions. Part of the conductive line is spanning across part of the first region of the first transistor and part of the second region of the second transistor.

Memory device having shared read/write data line for 2-transistor vertical memory cell

Methods of forming a transistor might include forming a dielectric overlying a semiconductor having a first conductivity type, forming a conductor overlying the dielectric, patterning the conductor and dielectric to define a gate stack of the transistor, forming a first extension region base and a second extension region base in the semiconductor, forming a first extension region riser overlying the first extension region base and forming a second extension region riser overlying the second extension region base, and forming a first source/drain region in the first extension region riser and forming a second source/drain region in the second extension region riser, wherein the first extension region base, the second extension region base, the first source/drain region, and the second source/drain region each have a second conductivity type different than the first conductivity type.

Apparatuses comprising transistors including extension regions

A microelectronic device includes a stack structure comprising a vertically alternating sequence of insulative and conductive structures arranged in tiers. At least one pillar, comprising a channel material, extends through the stack structure. A source region, below the stack structure, comprises a doped material with vertical extensions that protrude to an interface with the channel material at an elevation proximate at least one source-side GIDL region. Slit structures extend through the stack structure to divide the structure into blocks of pillar arrays. A series of spaced, discrete pedestal structures are included along a base of the slit structures. Forming the microelectronic device structure may include forming a lateral opening through cell materials of the pillar, vertically recessing the channel material, and laterally recessing other material(s) of the pillar before forming the doped material in the broadened recesses. Additional microelectronic devices, related methods, and electronic systems are also disclosed.

Microelectronic devices with vertically recessed channel structures and discrete, spaced inter-slit structures, and related methods and systems

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first data line located in a first level of the apparatus; a second data line located in a second level of the apparatus; a first memory cell located in a third level of the apparatus between the first and second levels, the first memory cell including a first transistor coupled to the first data line, and a second transistor coupled between the first data line and a charge storage structure of the first transistor; and a second memory cell located in a fourth level of the apparatus between the first and second levels, the second memory cell including a third transistor coupled to the second data line, and a fourth transistor coupled between the second data line and a charge storage structure of the third transistor, the first transistor coupled in series with the third transistor between the first and second data lines.

Memory device having 2-transistor vertical memory cell and shared channel region

A semiconductor device comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, and a channel structure within an opening vertically extending through the stack and comprising a first semiconductor material having a first band gap. The semiconductor device also comprises a conductive plug structure within the opening and in direct contact with the channel region, and a band offset structure within the opening and in direct physical contact with the channel structure and the conductive plug structure. The band offset structure comprises a second semiconductor material having a second band gap different than the first band gap. The semiconductor device further comprises a conductive line structure electrically coupled to the conductive plug structure. A method of forming a semiconductor device and an electronic system are also described.

Apparatuses including band offset materials, and related memory devices

Apparatus having a transistor connected between a voltage node and a load node, where the transistor includes a dielectric material overlying a semiconductor material including fins and having a first conductivity type, a conductor overlying the dielectric material, first and second extension region bases formed in the semiconductor material and having a second conductivity type, first and second extension region risers formed overlying respective first and second extension region bases and having the second conductivity type, and first and second source/drain regions formed in respective first and second extension region risers and having the second conductivity type at greater conductivity levels than their respective extension region risers, as well as method of forming similar transistors.

Transistors with raised extension regions and semiconductor fins

A microelectronic device comprises a conductive line and a transistor adjacent to the conductive line. The transistor comprises a channel material extending into the conductive line, the channel material contacting the conductive line in three dimensions, a dielectric material adjacent to the channel material, a conductive material adjacent to the dielectric material, and a passivation material adjacent to the channel material. The microelectronic device further comprises a conductive contact adjacent to the channel material, the conductive contact including a portion extending between opposing portions of the channel material. Related microelectronic devices, electronic devices, and related methods are also disclosed.

Devices including channel materials and passivation materials

A transistor comprises a 2D material structure and a gate structure. The 2D material structure conformally extends on and between surfaces of dielectric fin structures extending in parallel in a first horizontal direction, and comprises a source region, a drain region, and a channel region positioned between the source region and the drain region in the first horizontal direction. The gate structure overlies the channel region of the 2D material structure and extends in a second horizontal direction orthogonal to the first horizontal direction. The gate structure is within horizontal boundaries of the channel region of the 2D material structure in the first horizontal direction. Microelectronic devices, memory devices, and electronic systems are also described.

String driver assemblies including two-dimensional materials, and related memory devices

A method used in forming a memory array, comprises forming a substrate comprising a conductive tier, an insulator etch-stop tier above the conductive tier, a select gate tier above the insulator etch-stop tier, and a stack comprising vertically-alternating insulative tiers and wordline tiers above the select gate tier. Etching is conducted through the insulative tiers, the wordline tiers, and the select gate tier to and stopping on the insulator etch-stop tier to form channel openings that have individual bottoms comprising the insulator etch-stop tier. The insulator etch-stop tier is penetrated through to extend individual of the channel openings there-through to the conductive tier. Channel material is formed in the individual channel openings elevationally along the insulative tiers, the wordline tiers, and the select gate tier and is directly electrically coupled with the conductive material in the conductive tier. Structure independent of method is disclosed.

Memory array and methods used in forming a memory array

Some embodiments include apparatuses and methods using a substrate, a pillar having a length perpendicular to the substrate, a first conductive plate, a second conductive plate, a memory cell located between the first and second conductive plates and electrically separated from the first and second conductive plates, and a conductive connection. The first conductive plate is located in a first level of the apparatus and being separated from the pillar by a first dielectric located in the first level. The second conductive plate is located in a second level of the apparatus and being separated from the pillar by a second dielectric located in the second level. The memory cell includes a first semiconductor material located in a third level of the apparatus between the first and second levels and contacting the pillar and the conductive connection, and a second semiconductor material located in a fourth level of the apparatus between the first and second levels and contacting the pillar.

Memory device having 2-transistor memory cell and access line plate

Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

Integrated assemblies having transistor body regions coupled to carrier-sink-structures; and methods of forming integrated assemblies

Some embodiments include apparatuses and methods of operating such apparatuses. One of such apparatuses includes a data line, a conductive region, and a memory cell including a first transistor and a second transistor. The first transistor includes a first channel region coupled to the data line and the conductive region, a charge storage structure, and a first gate. The second transistor includes a second channel region coupled to the data line and the charge storage structure, and a second gate. The first gate is electrically separated from the second gate and opposite from the second gate in a direction from the first channel region to the second channel region.

Memory device having 2-transistor vertical memory cell and separate read and write gates

Growing community of inventors

Boise, ID, United States of America

Haitao Liu