Apple Inc.

Research in Motion Corporation

Blackberry Corporation

Palm, Incorporated

Haining Zhang

Saurabh Garg

Karan Sanghi

Vladislav V Petkov

Risvan Coskun

Ming Hu

Luis Pablo Estable

Robert D Oliver

Wen Zhao

Xin Jin

Xueting Liu

Radha Kumar Pulyala

Muhammad Khaledul Islam

Maxime M Matton

Richard M Solotke

Syed Aon Mujtaba

Johnson O Sebeni

Jianxiong Shi

Arun Godfrey Mathias

Kee-Bong Song

Mitchell David Adler

Dallas Blake De Atley

Christian W Mucke

Isabel Mahe

Jonathan Jay Andrews

Anand Dalal

William Burchill

Jerry Hauck

Jason D Gosnell

Arjuna Sivasithambaresan

Aon Mujtaba

Stephen Schell

Alex Ho

Munammad Khalecul Islam

Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.

Methods and apparatus for synchronizing uplink and downlink transactions on an inter-device communication link

Methods and apparatus for registering and handling access violations of host memory. In one embodiment, a peripheral processor receives one or more window registers defining an extent of address space accessible from a host processor; responsive to an attempt to access an extent of address space outside of the extent of accessible address space, generates an error message; stores the error message within a violation register; and resumes operation of the peripheral processor upon clearance of the stored error message.

Memory access protection apparatus and methods for memory mapped access between independently operable processors

Methods and apparatus for locking at least a portion of a shared memory resource. In one embodiment, an electronic device configured to lock at least a portion of a shared memory is disclosed. The electronic device includes a host processor, at least one peripheral processor and a physical bus interface configured to couple the host processor to the peripheral processor. The electronic device further includes a software framework that is configured to: attempt to lock a portion of the shared memory; verify that the peripheral processor has not locked the shared memory; when the portion of the shared memory is successfully locked via the verification that the peripheral processor has not locked the portion of the shared memory, execute a critical section of the shared memory; and otherwise attempt to lock the at least the portion of the shared memory at a later time.

Methods and apparatus for locking at least a portion of a shared memory resource

Methods and apparatus for an inter-processor communication (IPC) link between two (or more) independently operable processors. In one aspect, the IPC protocol is based on a 'shared' memory interface for run-time processing (i.e., the independently operable processors each share (either virtually or physically) a common memory interface). In another aspect, the IPC communication link is configured to support a host driven boot protocol used during a boot sequence to establish a basic communication path between the peripheral and the host processors. Various other embodiments described herein include sleep procedures (as defined separately for the host and peripheral processors), and error handling.

Methods and apparatus for running and booting an inter-processor communication link between independently operable processors

Methods and apparatus for limiting wake requests from one device to one or more other devices. In one embodiment, the requests are from a peripheral processor to a host processor within an electronic device such as a mobile smartphone or tablet which has power consumption requirements or considerations associated therewith. In one implementation, the peripheral processor includes a wake-limiting procedure encoded in e.g., its software or firmware, the procedure mitigating or preventing continuous and/or overly repetitive 'wake' requests from the peripheral processor.

Apparatus and methods for wake-limiting with an inter-device communication link

Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.

Methods and apparatus for reduced-latency data transmission with an inter-processor communication link between independently operable processors

Methods and apparatus for managing power with an inter-processor communication link between independently operable processors

Methods and apparatus for enabling a peripheral processor to retrieve and load firmware for execution within the constraints of its memory. The peripheral processor is allocated a portion of the host processor's memory, to function as a logical secondary and tertiary memory for memory cache operation. The described embodiments enable the peripheral processor to support much larger and more complex firmware. Additionally, a multi-facetted locking mechanism is described which enables the peripheral processor and the host processor to access the secondary memory, while minimally impacting the other processor.

Methods and apparatus for loading firmware on demand

Methods and apparatus for running and booting inter-processor communication link between independently operable processors

The disclosed embodiments provide a system that uses a first antenna and a second antenna in a portable electronic device. During operation, the system receives a request to switch from the first antenna to the second antenna to transmit a signal to a cellular receiver. Next, the system loads a set of radio-frequency (RF) calibration values for the second antenna. Finally, the system performs the switch from the first antenna to the second antenna to transmit the signal, wherein the second antenna is operated using the RF calibration values after the switch.

Facilitating switching between transmitting antennas in portable electronic devices

Apparatus for managing power and running and booting an inter-processor communication link between independently operable processors

Growing community of inventors

Cupertino, CA, United States of America

Haining Zhang