Western Digital Technologies, Inc.

Sandisk Technologies Inc.

Haining Liu

Yun-Tzuo Lai

Yuriy Pavlenko

Subhash Balakrishna Pillai

YungLi Ji

Ming-Yu Tai

Parvaneh Alavi

George G Artnak, Jr

Scott Jinn

Kai-Lung Cheng

Caesar Cheuk-Chow Cheung

Jerry Lo

Hung-Cheng Yeh

Hung-min Chang

Yung-Li Ji

Sergey Anatolievich Gorobets

Richard David Barndt

Aldo Giovanni Cometti

Neil David Hutchison

Siddharth Choudhuri

A data storage device processes a mixed workload including a plurality of superblocks to be written to and read from a plurality of memory dies, where each of the plurality of superblocks to be apportioned among the plurality of memory dies. The data storage device writes a first data stripe associated with a first superblock to the plurality of memory dies according to a sequential write pattern, and reads the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern. The sequential write pattern causes the controller to write to the plurality of memory dies in a first order of memory dies. The sequential read pattern causes the controller to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, thereby reducing read collisions.

Read collision avoidance in sequential mixed workloads

A data storage device that provides priority-based internal data movement includes a controller communicatively coupled to volatile memory and to non-volatile memory circuits, where the controller is configured to queue requests in a plurality of queues in the volatile memory, where each of the requests is associated with one of a plurality of internal data movement command types. The controller is also configured to select one of the plurality of queues based on a prioritization of the plurality of internal data movement command types. The controller is also configured to determine that the selected queue includes at least one request of the associated internal data movement command type. The controller is also configured to issue the at least one request from the selected queue to at least one of the non-volatile memory circuits.

Priority-based data movement

The subject technology provides for managing a data storage system. Commands are identified into as a first command type or a second command type. The commands identified as the first command type are assigned to a first queue, and the commands identified as the second command type are assigned to a second queue. After the commands from the first queue and the commands from the second queue are processed based on a scheduling ratio over a predetermined period of time, a write amplification factor, number of host read commands, and number of host write commands during the predetermined period of time are determined. The scheduling ratio is updated based on the write amplification, the number of host read commands, the number of host write commands, and a predetermined scheduling ratio factor. Subsequent commands are processed from the first queue and the second queue based on the updated scheduling ratio.

Dynamic command scheduling for storage system

A device that provides error recovery handling includes a processor that is configured to receive an error recovery request including error type information and a page address, where the error type information is mapped to a first error recovery technique. The processor may be configured to determine whether an error count associated with the flash memory circuit satisfies a first criterion and an error map associated with the flash memory circuit satisfies a second criterion, where the error count indicates a number of read errors that have occurred and the error map indicates blocks in which the read errors have occurred. The processor may be configured to utilize a second technique to attempt to recover data when the first and second criterions are satisfied, otherwise utilize the first technique to attempt to recover data, where the second technique is associated with recovering data stored in an offline flash memory circuit.

Error recovery handling

Systems and methods are disclosed for scheduling access commands for a data storage device. A data storage device determines a layout of a plurality of non-volatile memory arrays. The data storage device also determine completed access statistics and pending access statistics for a first set of the plurality of non-volatile memory arrays during a monitoring period. The data storage device further generates a schedule based on the layout of the plurality of non-volatile memory arrays, the completed access statistics, and the pending access statistics and executes access commands based on schedule.

Scheduling access commands for data storage devices

The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.

Recovery of validity data for a data storage system

Command scheduling for die sets of non-volatile memory may be performed based on command states of the die sets. Upon receiving an erase command to erase data stored in a first block set of non-volatile memory, a command state of the first die set of the non-volatile memory is determined, where the first die set contains the first block set. If the first die set is determined to be in a pending command state, the erase command is queued in a wait queue. If the first die set is determined to be in an idle command state, the erase command is scheduled to erase the data stored in the first block set.

Geometry-aware command scheduling

A storage device may include a controller and a memory array including a plurality of dies arranged into a plurality of channels. In some examples, the controller may be configured to define, from the memory array, a plurality of die-sets based on respective chip enable lines associated with the plurality of dies, wherein each die-set of the plurality of die-sets includes at least one die from each of the plurality of channels; define, from a selected die-set of the plurality of die-sets, a plurality of blocksets, wherein each blockset includes a block from each die of the selected die-set; receive a unit of data to be stored; and issue commands that cause the unit of data to be stored in blocks of a selected blockset of the plurality of blocksets.

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Irvine, CA, United States of America

Haining Liu