Altera Corporation

Haiming Yu

Wei Yee Koay

Hao-Yuan Howard Chou

Tony K Ngai

Ray Ruey-Hsien Hu

Wei Zhang

Kok Heng Choe

Andy Louie Lee

David Lewis

Jeffrey T Watt

Yanzhong Xu

Teng Chow Ooi

Catherine Chingi Chang

A first-in-first-out memory may have first and second memory banks. A write controller may write data into the first and second memory banks. In performing write operations, the write controller may determine whether to write the data into the first bank or the second bank by evaluating a first bank empty flag and a second bank empty flag. When transitioning between writing in the first bank and the second bank, the write controller may latch a write address value indicative of the last location at which valid data was written in a given bank. A read controller may read data from the first and second memory bank. The read controller may determine when to transition between reading in the first bank and reading in the second bank by comparing a current read address to the latched write address value.

First-in-first-out memory with dual memory banks

Integrated circuits with memory elements are provided. Data may be loaded into the memory elements using write driver circuitry. The write driver circuitry may be provided with a fixed positive power supply voltage and an time-varying ground power supply voltage that is less than the positive power supply voltage. The time-varying ground power supply voltage may be generated using programmable power supply circuitry. The programmable power supply circuitry may include a pulse generation circuit and a configurable capacitive circuit. The pulse generation circuit may output a pulse signal to the capacitive circuit. In response to receiving the pulse signal, the capacitive circuit may push the time-varying ground power supply voltage to a negative value. The time-varying ground power supply voltage may be driven below zero volts for at least a portion of a write cycle to help improve write margins and increase memory yield.

Negative bit line driver circuitry

An integrated circuit with memory elements is provided. The memory elements may be single-port memory cells that are used to provide multiport memory functionality. The integrated circuit may include an arbitration circuit operable to receive memory access requests from at least first and second request generators. The arbitration circuit may be configured to operate in a synchronous mode and an asynchronous mode. The arbitration circuit operating in the synchronous mode may perform port selection based on a predetermined logic table. The arbitration circuit operating in the asynchronous mode may execute a memory request as soon as it is received by the arbitration circuit. Requests received while a current memory access is being performed may be put on hold until the current memory access has been completed.

Memory arbitration circuitry

Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. The access transistors may have gates that are controlled by an address signal. The address signal may be asserted during read/write operations to turn on the access transistors so that read/write data can be passed through the access transistors. The voltage level to which the address signal is raised during read/write operations may be adjusted using programmable voltage biasing circuitry. A number of integrated circuits may be tested during device characterization procedures to determine the amount by which the address signal should be adjusted using the programmable voltage biasing circuit so that the memory elements in the integrated circuits satisfy design criteria.

Programmable addressing circuitry for increasing memory yield

A method for a read-before-write functionality for a memory within a programmable logic device (PLD) is provided. The method begins when a read operation and a write operation are initiated through two different ports of a memory simultaneously to access the same address in the memory. In order to prevent the write operation from proceeding prior to the read operation, a read-before-write control logic is provided to the control block of the port that supports the write operation. Thus, the write operation is paused until the control block of the port that supports the write operation receives a signal from a read sense amplifier indicating that the read operation is complete. The read sense amplifier is capable of detecting the completion of a read operation by monitoring the voltage difference of the read bitline. When this voltage difference reaches a threshold value, the read sense amplifier triggers a write wordline signal. The enabling of the write wordline signal causes, the data to be written to the memory.

Dual port PLD embedded memory block to support read-before-write in one clock cycle

A memory circuit, where data is read from and written to the memory cell in one clock cycle via a port without pre-charging the port between reading data from and writing data to the memory cell via the port in the one clock cycle, is described. In one aspect, an embodiment of the present invention provides a memory circuit with a write control switch that has a voltage drop of substantially zero volts. In another aspect, an embodiment of the present invention provides a memory circuit with a write driver that uses a complementary metal oxide semiconductor ('CMOS') inverter whose P-channel MOS ('PMOS') transistor size is approximately 0.5 times its N-channel MOS (&#x201c;NMOS&#x201d;) transistor size. In yet another aspect, an embodiment of the present invention provides a memory circuit with a latch-type read sense amplifier.

Reading and writing data to a memory cell in one clock cycle

A memory unit includes width decoding logic enabling data to be accessed in a memory array at different data widths. To improve memory access speed, the memory unit also includes dedicated read output paths for accessing data at the full data width of the memory array. The dedicated read output paths bypass the width decoding logic and provide data from the memory array directly to a data bus, thereby providing improved memory performance when width decoding is not needed. The memory unit can be incorporated in programmable devices and a programmable device configuration can select either the read bypass paths or the width decoding logic. Hardware applications that require width decoding and improved memory access speed can utilize additional programmable device resources outside the memory unit to register the full width data from the memory unit and convert it to a different data width.

Using dedicated read output path to reduce unregistered read access time for a FPGA embedded memory

Dual port memory array circuitry is provided that includes bit line voltage clamping circuitry. The clamping circuitry contains control transistors that are used to enable and disable the clamping circuitry. The clamping circuitry also contains voltage regulator transistors and feedback paths. When a write operation is performed on one port of the dual port memory array while a read operation is being performed on the other port of the dual port memory array, the bit line voltage clamping circuitry prevents the voltages on the read port bit lines from dropping too low. This allows the write operation to be performed rapidly, even if the memory cell being written to has been adversely affected by variations due to process, voltage, and temperature.

Dual port random-access-memory circuitry

Systems and methods are provided for computing write margins for dual-port memory. A design for a dual-port memory array cell is generated using a circuit design tool. A user modifies the design of the dual-port memory array cell to incorporate two voltage sources. The voltage sources are used to represent differential noise on the memory cell. A write margin calculation tool uses a circuit simulation tool to perform transient simulations of write-during-read operations on the modified dual-port memory array cell. During the transient simulations, the voltage level on the voltages sources is systematically varied. The write margin for the dual-port memory is determined by analyzing the results of the transient simulations for each of the voltage levels used for the voltage sources.

Write margin calculation tool for dual-port random-access-memory circuitry

Integrated circuits such as programmable logic device integrated circuits are provided that have memory arrays that may be configured for true dual port operation or simple dual port operation. The memory arrays include memory cells arranged in rows and columns and associated row address lines and data lines. Sense amplifiers and write drivers are used for reading and writing data. Precharge drivers are used to precharge the data lines prior to read operations. Configurable multiplexer circuitry in the array has read paths through which data is provided to the sense amplifiers from the memory cells. The multiplexer circuitry has write paths through which data from the write drivers is written into the memory cells. The read paths and the write paths contain no more than a single pass gate each. Each precharge driver may be connected to a respective one of the data lines with no intervening pass gates.

Configurable random-access-memory circuitry

Using dedicated read output path to reduce unregistered read access time for FPGA embedded memory

Dual port memory blocks that have a reduced layout area are provided. The write drivers and sense amplifiers are shared between the dual ports to reduce the number of write drivers and sense amplifiers to save layout area. The write drivers for the two ports are used to write into all of the first port's bitlines. The sense amplifiers for the two ports are used to read from all of the second port's bitlines. A memory block can to support true dual port (TDP) and simple dual port (SDP) operation using substantially less write drivers and sense amplifiers.

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San Jose, CA, United States of America

Haiming Yu