International Business Machines Corporation

Haim Kermany

Alexander Ivrii

Ziv Nevo

Avi Ziv

Raviv Gal

Elena Guralnik

A method, and apparatus and a computer program product for determining coverage in hardware verification based on relations between coverage events. The method comprises generating an over-approximation model of the hardware being verified to perform formal verification thereof with respect to a target coverage event being utilized in the verification process along with a set of coverage events. A score indicating an estimated conditional probability to hit the target coverage event in the verification process, given that the coverage event is hit in the verification process, may be determined for each coverage event based on the formal verification. The method further comprises selecting test suits to be executed in the verification process based on the scores and the test suits probability to hit each coverage event. The verification process may be the performed the selected test suits in order to cover the target coverage event.

Hardware verification based on relations between coverage events

A computerized method for mapping of electronic designs comprising using at least one hardware processor for receiving a first hardware design model and a second hardware design model, each hardware design model configured to receive a startup state and send digital output values. Hardware processor(s) are used for generating a plurality of initial states. Hardware processor(s) are used for computing, using each one of the first and second hardware design models, at least one specific output value for each one of the plurality of initial states. Hardware processor(s) are used for selecting corresponding initial states that produce equivalent at least one specific output value between the first hardware design model and the second hardware design model. Hardware processor(s) are used for storing the selected corresponding initial states as mappings between the first hardware design model and the second hardware design model.

Verifying sequential equivalence for randomly initialized designs

A computer-implemented method, computerized apparatus and computer program product. The method includes receiving at a computing device, a Sweeney-Robertson-Tocher (SRT) implementation, and a look-up table (LUT) used by the SRT implementation; obtaining an assertion for the SRT, the assertion associated with at least one entry from the LUT; verifying the assertion by executing a formal verification engine on the SRT implementation. Subject to the assertion failing, the method further provides a counter example for a computation that when performed by the SRT implementation accesses the at least one entry. Further, subject to the assertion holding, the method performs determining that the at least one entry is unreachable.

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Manof, Israel

Haim Kermany