Texas Instruments Corporation

Haim Horovitz

Sameer P Pendharkar

Lily Springer

Robert Graham Shaw

Wen-Hwa M Chu

Paul C Mannas

Mark Allenspach

Peter Fleischmann

Validation of at least some of a proposed semiconductor design layout is disclosed. According to one or more aspects of the present invention, a first voltage dependent design rule is applied to an edge of an area of the layout if the edge is not covered by a pseudo layer. A second voltage dependent design rule is, on the other hand, applied to the edge of the area if the edge is covered by the pseudo layer.

Edge recognition based high voltage pseudo layer verification methodology for mix signal design layout

A technique for checking a layout design of an integrated circuit is disclosed. The technique has application to converting the design of a circuit from schematic to layout form. Instances where multiple pwell isolation tanks are coupled to the same node and where one or more pwell isolation tanks are shorted to a substrate are detected. Node breakers are inserted in the layout between pwell isolation tanks coupled to the same node and between the substrate and isolated pwell tanks coupled to the substrate. The node breakers are inserted in the circuit schematic as well to satisfy a layout versus schematic comparison. Inserting the node breakers highlights circuit component groupings as well as which tanks contain certain elements, if any. This allows designers to make a conscious decision as to the location and groupings of elements in a layout design.

Isolated pwell tank verification using node breakers

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Los Altos, CA, United States of America

Haim Horovitz