Infineon Technologies Ag

Intel Corporation

Haim Granot

Alexander Gendler

Igor Yanover

Gavri Berger

Lev Makovsky

Elkana Korem

Daniela Kaufman

Hanan Shomroni

Edo Hachamo

Yoav Lavi

Meny Yanni

Rivka Blum

Anat Hershko

Georgiy Shenderovitch

Eran Weingatren

Elliot Cohen

Gil Naveh

Eyal Rosin

Eran Weingarten

Regis Hervigo

Robert Knuth

Amnon Rom

In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

Adjusting a throttling threshold in a processor

The present invention is a system in which a multiplicity of diverse dedicated hardware off-core execution units are connected to a core processor in order to increase the speed, power, and flexibility of the processor, and a method of operating the system. Reference instructions executed by the core processor initiate the execution of Configurable Long Instruction Word (CLIW) instructions stored in a CLIW memory. The operation of the off-core execution units is controlled by CLIW instructions. These CLIW instructions may also control operations performed by the core processor, and may be in addition to any other CLIW instructions that control the core processor exclusively. The off-core logic units are operationally connected to the data memory of the core processor under the control of the core processor's data address logic. The use of CLIW technology for the control of the off-core hardware logic units allows the addition of a plurality of diverse off-core logic units without affecting the instruction set, coding space, or instruction decoders of the core processor.

Method and apparatus for adding user-defined execution units to a processor using configurable long instruction word (CLIW)

A method for executing instructions in a data processor and improvements to data processor design, which combine the advantages of regular processor architecture and Very Long Instruction Word architecture to increase execution speed and ease of programming, while reducing power consumption. Instructions each consisting of a number of operations to be performed in parallel are defined by the programmer, and their corresponding execution unit controls are generated at compile time and loaded prior to program execution into a dedicated array in processor memory. Subsequently, the programmer invokes reference instructions to call these defined instructions, and passes parameters from regular instructions in program memory. As the regular instructions propogate down the processor's pipeline, they are replaced by the appropriate controls fetched from the dedicated array in processor memory, which then go directly to the execution unit for execution. These instructions may be redefined while the program is running. In this way the processor benefits from the speed of parallel processing without the chip area and power consumption overhead of a wide program memory bus and multiple instruction decoders. A simple syntax for defining instructions, similar to that of the C programming language is presented.

Configurable long instruction word architecture and instruction set

A processor for performing a block floating point Fast Fourier Transform having improved signal to quantization noise ratio performance. In the radix-2 Decimation In Time algorithm, overflow between stages is prevented by a scale down by two invoked by comparison with a fixed comparison constant. Unfortunately, the fixed comparison constant is not always optimum for maximizing the signal to quantization noise ratio, which is degraded by excessive scale down. Moreover, current mechanisms are limited to the radix-2 block floating point FFT. The processor of the present invention provides the programmer with a FFT compare register which is loadable under program control, thus allowing the programmer to adjust the threshold at which scale down of the stage output is activated for better control over the signal to quantization noise ratio. In addition, the present invention supports other FFT structures besides the radix-2 block floating point FFT.

Mechanism for block floating point FFT hardware support on a fixed point digital signal processor

Growing community of inventors

Bat Hefer, Israel

Haim Granot