Advanced Micro Devices Corporation

Globalfoundries Inc.

Rubrik, Inc.

Spansion Llc.

Innovative Foundry Technologies B.v.

Haihong Wang

Bin Yu

Shibly S Ahmed

Qi Xiang

Zoran Krivokapic

Judy Xilin An

Ming-Ren Lin

Eric N Paton

Srikanteswara Dakshina-Murthy

Minh Van Ngo

Paul Raymond Besser

Cyrus E Tabery

Jung-Suk Goo

Olov B Karlsson

Krishnashree Achuthan

Matthew S Buynoski

Ming Lin

Wiley Eugene Hill

Witold P Maszara

Chih-Yuh Yang

Minh-Van Ngo

Gopikrishnan Aditya Suresh

Yider Wu

Joong Jeon

Systems and methods to throttle a universal backup host are described. The system executes a job, at a backup host, to back up a file set from a source host including fetching metadata from the source host. The system identifies a first operation set from operation sets, the operation set including a first operation. The system communicates, in parallel, requests for metadata items, over a network, to the source host, receives responses, and processes the responses by utilizing threads from a thread pool. The system generates latencies, counts the number of requests, and stores the latencies and number of requests in samples. The system aggregates the samples responsive to a timeout. The system resizes the thread pool based on the aggregating. Finally, the system backs up the file set from the source host based on the metadata.

Adaptive throttling in a universal backup host

Systems and methods to throttle a universal backup host are described. The system receives responses, over a network, corresponding to one or more requests by utilizing one or more threads from a thread pool. The threads include a first thread. The requests include a first request. The receiving the responses includes receiving a first response corresponding to the first request by utilizing the first thread, the first response includes a first metadata item. The system processes the responses by generating a first latency based on the first response and incrementing a number for registering requests based on the first response. Next, the system aggregates samples. The samples include the first latency and the number of requests. Next, the system resizes the thread pool based on the aggregating and backs up the file set from the source host based on the metadata.

A double gate metal-oxide semiconductor field-effect transistor (MOSFET) includes a fin, a first gate and a second gate. The first gate is formed on top of the fin. The second gate surrounds the fin and the first gate. In another implementation, a triple gate MOSFET includes a fin, a first gate, a second gate, and a third gate. The first gate is formed on top of the fin. The second gate is formed adjacent the fin. The third gate is formed adjacent the fin and opposite the second gate.

Double and triple gate MOSFET devices and methods for making same

A double gate germanium metal-oxide semiconductor field-effect transistor (MOSFET) includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, and a second gate formed adjacent a second side of the germanium fin opposite the first side. A triple gate MOSFET includes a germanium fin, a first gate formed adjacent a first side of the germanium fin, a second gate formed adjacent a second side of the germanium fin opposite the first side, and a top gate formed on top of the germanium fin. An all-around gate MOSFET includes a germanium fin, a first sidewall gate structure formed adjacent a first side of the germanium fin, a second sidewall gate structure formed adjacent a second side of the germanium fin, and additional gate structures formed on and around the germanium fin.

Germanium MOSFET devices and methods for making same

A double-gate semiconductor device includes a substrate, an insulating layer, a fin and two gates. The insulating layer is formed on the substrate and the fin is formed on the insulating layer. A first gate is formed on the insulating layer and is adjacent a first sidewall of the fin. The second gate is formed on the insulating layer and is adjacent a second sidewall of the fin opposite the first sidewall. The first and second gates both include a conductive material and are electrically separated by the fin.

Double-gate semiconductor device with gate contacts formed adjacent sidewalls of a fin

A method may include forming a gate electrode over a fin structure, depositing a first metal layer on a top surface of the gate electrode, performing a first silicide process to convert a portion of the gate electrode into a metal-silicide compound, depositing a second metal layer on a top surface of the metal-silicide compound, and performing a second silicide process to form a fully-silicided gate electrode.

Fully silicided gate structure for FinFET devices

A device includes a fin, a first gate and a second gate. The first gate is formed adjacent a first side of the fin and includes a first layer of material having a first thickness and having an upper surface that is substantially co-planar with an upper surface of the fin. The second gate is formed adjacent a second side of the fin opposite the first side and includes a second layer of material having a second thickness and having an upper surface that is substantially co-planar with the upper surface of the fin, where the first thickness and the second thickness are substantially equal to a height of the fin.

A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a ALD process.

Method of forming isolation regions for integrated circuits

An exemplary embodiment relates to a method for forming a metal oxide semiconductor field effect transistor (MOSFET). The method includes providing a substrate having a gate formed above the substrate and performing at least one of the following depositing steps: depositing a spacer layer and forming a spacer around a gate and gate insulator located above a layer of silicon above the substrate; depositing an etch stop layer above the spacer, the gate, and the layer of silicon; and depositing a dielectric layer above the etch stop layer. At least one of the depositing a spacer layer, depositing an etch stop layer, and depositing a dielectric layer comprises high compression deposition which increases in tensile strain in the layer of silicon.

Tensile strained substrate

A semiconductor device includes a group of fin structures. The group of fin structures includes a conductive material and is formed by growing the conductive material in an opening of an oxide layer. The semiconductor device further includes a source region formed at one end of the group of fin structures, a drain region formed at an opposite end of the group of fin structures, and at least one gate.

FinFET device with multiple fin structures

A method includes forming a first rectangular mesa from a layer of semiconducting material and forming a first dielectric layer around the first mesa. The method further includes forming a first rectangular mask over a first portion of the first mesa leaving an exposed second portion of the first mesa and etching the exposed second portion of the first mesa to produce a reversed T-shaped fin from the first mesa.

Reversed T-shaped finfet

A method for forming fin structures for a semiconductor device that includes a substrate and a dielectric layer formed on the substrate is provided. The method includes etching the dielectric layer to form a first structure, depositing an amorphous silicon layer over the first structure, and etching the amorphous silicon layer to form second and third fin structures adjacent first and second side surfaces of the first structure. The second and third fin structures may include amorphous silicon material. The method further includes depositing a metal layer on upper surfaces of the second and third fin structures, performing a metal-induced crystallization operation to convert the amorphous silicon material of the second and third fin structures to a crystalline silicon material, and removing the first structure.

Systems and methods for forming multiple fin structures using metal-induced-crystallization

A method of manufacturing an integrated circuit (IC) utilizes a shallow trench isolation (STI) technique. The shallow trench isolation technique is used in strained silicon (SMOS) process. The liner for the trench is formed from a semiconductor or metal layer which is deposited in a low temperature process which reduces germanium outgassing. The low temperature process can be a CVD process.

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Fremont, CA, United States of America

Haihong Wang