Semiconductor Manufacturing International (shanghai) Corporation

Monolithic Power Systems, Inc.

Semiconductor Manufacturing International (beijing) Corporation

Haifeng Yang

Fei Liu

Hua Tang

Ji-Hyoung Yoo

Benpeng Xun

Chia Chi Yang

Joel McGregor

Jeesung Jung

Deming Xiao

Ze-Qiang Yao

Ben Peng Xun

Meng Meng Guo

Mengmeng Guo

A manufacturing process of a DMOS device in a drift region in a semiconductor substrate, having: forming a polysilicon layer above the drift region; forming a block layer above the polysilicon layer; etching both the block layer and the polysilicon layer, through a window of a first masking layer to expose a window to the drift region; implanting dopants through the window to the drift region to form a body region; forming blocking spacers to wrap side walls of the polysilicon layer; implanting dopants into the body region under a window shaped by the blocking spacers to form a body pickup region; etching away the blocking spacers; performing a masking step to form gates; forming ONO spacers to wrap side walls of the gates; and performing a masking step to form source regions and drain pickup regions.

Manufacturing method of self-aligned DMOS body pickup

The present disclosure provides circuits and methods for generating clock-signals. An exemplary clock-signal generation circuit includes a delay buffer unit; an inverter unit coupled to the delay buffer unit; a first delay unit having a first NAND Boolean calculation sub unit, a first sub delay unit and a first level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a first delayed clock-signal; and a second delay unit having a second NAND Boolean calculation sub unit, a second sub delay unit and a second level shift unit sequentially connected in serial, coupled to the inverter unit and configured for generating a second delayed clock signal.

Circuit and method for generating clock-signals

The present disclosure provides asynchronous successive approximation register analog-to-digital converter (ASAR ADC) circuits and signal conversion method thereof. An exemplary ASAR AC circuit includes a sample/hold circuit configured to input a first analog signal and output a second analog signal; a digital-to-analog converter circuit configured to output a third analog signal; a first voltage comparison circuit configured to respond to a valid level of a latch signal, and output a first logic level and a second logic level; a first logic circuit configured to respond to a valid level of a flag signal, and identify a comparison result of the first voltage comparison circuit and output the first digit signal; and a pulse generation circuit configured to generate the latch signal and the flag signal with a generation time of the valid levels independently from the first logic level and the second logic level.

ASAR ADC circuit and conversion method thereof

The present disclosure provides an asynchronous successive approximation register analog-to-digital conversion (ASAR ADC) circuit, including: a comparator circuit, an XOR gate circuit, an ASAR logic circuit, a metastable state detection (MD) circuit, a capacitor, and a digital-to-analog converter (DAC) circuit. The comparator circuit has a first input terminal connected to an analog signal, a first output terminal of the comparator circuit respectively connected to a first input terminal of the ASAR circuit and a first input terminal of the XOR gate circuit, a second output terminal of the comparator circuit respectively connected to a second input terminal of the ASAR gate circuit and a second input terminal of the XOR gate circuit, and an enable signal input terminal connected to a control signal output terminal of the ASAR logic circuit. The XOR gate circuit has an output terminal connected to a third input terminal of the ASAR logic circuit.

Asynchronous successive approximation register analog-to-digital converter circuit and method for configuring the same

Method of forming dual gate insulation layers and semiconductor device having dual gate insulation layers is disclosed. The method of forming dual gate insulation layers comprises forming a first thin layer of a thick gate insulation layer on a semiconductor substrate by oxidizing the semiconductor substrate, depositing a second thicker layer of the thick gate insulation layer on the first thin layer, removing a portion of the thick gate insulation layer to expose a surface area of the semiconductor substrate and forming a thin gate insulation layer on the exposed surface area of the semiconductor substrate. The method of forming dual gate insulation layers, when applied in fabricating semiconductor devices having dual gate insulation layers and trench isolation structures, may help to reduce a silicon stress near edges of the trench isolation structures and reduce/alleviate/prevent the formation of a leaky junction around the edges of the trench isolation structures.

Method for forming dual gate insulation layers and semiconductor device having dual gate insulation layers

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Shanghai, China

Haifeng Yang