Globalfoundries Inc.

Haifeng Sheng

Jinping Liu

Jiehui Shu

Haigou Huang

Huang Liu

Daniel J Jaeger

Huy Cao

Xintuo Dai

Hui Zang

Garo Jacques Derderian

Haiting Wang

Andy C Wei

Laertis Economikos

Guillaume Bouche

Ravi Prakash Srivastava

Zhiguo Sun

Bharat V Krishnan

Jinsheng Gao

Qiang Fang

Chih-Chiang Chang

Pei Liu

Chang Ho Maeng

Fuad H Al-Amoody

Kenneth Andrew Bates

Tai Fong Chao

David Michael Permana

Shyam Pal

Xingzhao Shi

Daniel Fisher

Anthony Ozzello

Ja-Hyung Han

SangWoo Lim

Dimitri R Kioussis

The present disclosure relates to methods for forming fill materials in trenches having different widths and related structures. A method may include: forming a first fill material in a first and second trench where the second trench has a greater width than the first trench; removing a portion of the first fill material from each trench and forming a second fill material over the first fill material; removing a portion of the first and second fill material within the second trench; and forming a third fill material in the second trench. The structure may include a first fill material in trenches having different widths wherein the upper surfaces of the first fill material in each trench are substantially co-planar. The structure may also include a second fill material on the first fill material in each trench, the second fill material having a substantially equal thickness in each trench.

Method of forming semiconductor material in trenches having different widths, and related structures

Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiOlayer; forming a metal layer over the SiOlayer; and planarizing the metal and SiOlayers down to the gate cap layer.

Siloxane and organic-based MOL contact patterning

A contact etch stop layer includes a nitride layer formed over a sacrificial gate structure and a polysilicon layer formed over the nitride layer. During subsequent processing, the polysilicon layer is adapted to oxidize and form an oxide layer. The oxidation of the polysilicon layer effectively shields the underlying nitride contact etch stop layer from oxidation, which protects the mechanical integrity of the nitride layer.

Contact etch stop layer with sacrificial polysilicon layer

The disclosure is directed to methods of planarizing an integrated circuit structure including: forming a dielectric over a first nitride layer; planarizing the dielectric to a top surface of a set of nitride fins in a first region and removing the dielectric from a second region to expose the substantially planar upper surface in a second region; forming a second nitride layer over the dielectric and the top surface of the set of nitride fins and over the substantially planar upper surface; planarizing the second nitride layer such that the second nitride layer in the second region is planar with the top surface of the dielectric and the set of nitride fins, and such that the second nitride layer is removed from the first region; and performing an etch such that the first nitride layer in the first region is planar with the first nitride layer in the second region.

Methods for nitride planarization using dielectric

A method of removing the CESL from small canyon TS structures of a MOSFET device while maintaining gate cap height and the resulting device are provided. Embodiments include providing two gates laterally separated over and perpendicular to a fin of a semiconductor device, each gate having sidewall spacers and a nitride cap; forming a conformal SiN CESL on bottom and side surfaces of a trench formed between opposing spacers between the gates; filling the trench with oxide; planarizing the spacers, nitride caps, oxide, and CESL; removing the oxide; forming a topological flat-SiN layer over the spacers, nitride caps, and CESL; removing the topological flat-SiN layer from side and bottom surfaces of the trench; removing the CESL and the topological flat-SiN layer down to a top surface of the spacers; and performing contact metallization.

Silicon nitride CESL removal without gate cap height loss and resulting device

Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.

Devices and methods of forming SADP on SRAM and SAQP on logic

Methods of lithographic patterning and structures formed by lithographic patterning. A hardmask layer is formed on a dielectric layer, a feature is formed on the hardmask layer, and a mandrel is formed that extends in a first direction across the first feature. The mandrel and the hardmask layer beneath the mandrel are removed to pattern the hardmask layer with the feature masking a section of the hardmask layer. After the hardmask layer is patterned, the dielectric layer is etched to form a first trench and a second trench that are separated by a section of the dielectric layer masked by the section of the hardmask layer. The first trench and the second trench are filled with a conductor layer to respectively form a first wire and a second wire that is separated from the first wire by the section of the dielectric layer.

Self-aligned lithographic patterning with variable spacings

One illustrative method disclosed herein includes forming a liner layer above a layer of spacer material, forming an ion-containing region in at least a portion of a first portion of the liner layer while not forming the ion-containing region in a second portion of the liner layer, performing a liner etching process on the first and second portions of the liner layer so as to remove the second portion of the liner layer while leaving at least a portion of the first portion of the liner layer positioned adjacent a gate structure and, with the first portion of the liner layer positioned adjacent the gate structure, performing at least one spacer formation anisotropic etching process on the layer of spacer material so as to define a spacer adjacent the gate structure.

Methods of forming spacers on FinFET devices

One illustrative method disclosed herein includes, among other things, forming a first sacrificial layer comprising amorphous silicon or polysilicon material around a fin in a lateral space between a plurality of laterally spaced apart gate structures that are positioned around the fin, performing a first selective etching process to remove a first sacrificial layer selectively relative to surrounding material so as to expose the fin in the lateral space, forming an epi material on the exposed portion of the fin, and forming a second layer of a sacrificial material above the epi material. The method also includes selectively removing the second layer of sacrificial material relative to at least the first layer of material to thereby define a source/drain contact opening that exposes the epi material and forming a self-aligned trench conductive source/drain contact structure that is conductively coupled to the epi material.

Methods of forming self-aligned contacts on FinFET devices

A method of fabricating a semiconductor device is provided. The method begins by providing a semiconductor device structure having electronic devices formed on a semiconductor substrate, and having an upper metal layer associated with electrical contacts for the electronic devices. The method continues by forming a diffusion barrier layer overlying the upper metal layer. Next, the method deposits a first layer of graded ultra-low-k (ULK) material overlying the diffusion barrier layer, a layer of ULK material overlying the first layer of graded ULK material, and a second layer of graded ULK material overlying the layer of ULK material. The method continues by depositing a layer of low temperature oxide material overlying the second layer of graded ULK material, and forming a layer of metal hard mask material overlying the layer of low temperature oxide material.

Method of fabricating a conductive interconnect arrangement for a semiconductor device

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Rexford, NY, United States of America

Haifeng Sheng