Shenzhen Microbt Electronics Technology Co., Ltd.

Haifeng Guo

Zuoxing Yang

Yuefeng Wu

Zhijun Fan

Weibin Ma

Lihong Huang

Yang Gao

Wenbo Tian

Qian Chen

Nan Li

Chao Xu

Jianbo Liu

Hongyan Ning

Fangyu Liu

Weixin Kong

Lianhua Duan

Chuan Gong

Hong Zhang

Guo Ai

Mo Chen

This disclosure relates to a method, an apparatus, and a data processing device for controlling a frequency search speed, the method for controlling the frequency search speed including: obtaining parameter information of a frequency search speed regulation gear; obtaining a frequency search parameter based on the parameter information of the frequency search speed regulation gear; and performing frequency search based on the obtained frequency search parameter.

Method, apparatus, data processing device, and medium for controlling frequency search speed

This application discloses a liquid cooling heat dissipation plate and a liquid cooling electronic device, wherein the liquid cooling heat dissipation plate includes a cooling plate unit, a liquid inlet and a liquid outlet are provided at side walls of the cooling plate unit, the liquid inlet is in connection with the liquid outlet through a penetrating channel, and the penetrating channel respectively penetrates two opposite mounting surfaces of the cooling plate unit; further, a pair of fin bases are respectively lapped at positions on the two mounting surfaces corresponding to the same straight channel, and the seal plate unit is lapped at a position on the mounting surface corresponding to positions in the penetrating channel that are not covered by the fin base; and any two of the fin base, the seal plate unit, and the mounting surface are fastened by friction welding.

Liquid cooling heat dissipation plate and liquid cooling electronic device

The present disclosure relates to a phase-locked loop circuit and a signal processing device. The phase-locked loop circuit includes: a charge pump configured with a charge pump current; and a loop filter connected to the charge pump and configured with a first resistance value, a first capacitance value, and a second capacitance value, wherein a zero frequency of the phase-locked loop circuit is configured to be determined by the first resistance value and the first capacitance value, and a pole frequency of the phase-locked loop circuit is configured to be determined by the first resistance value and the second capacitance value; wherein at least two of the charge pump current, the first resistance value, the first capacitance value, and the second capacitance value are adjustable, to change a loop bandwidth of the phase-locked loop circuit, to maintain a first ratio between the zero frequency and the loop bandwidth unchanged, and to maintain a second ratio between the pole frequency and the loop bandwidth unchanged.

Phase-locked loop circuit and signal processing device

Embodiments of this application provide a chip frequency control method and apparatus, a blockchain server, and a storage medium. The method includes: determining a real-time computing power ratio of a chip of a blockchain server, a real-time temperature of the chip, and a real-time voltage of the chip; and adjusting a setting frequency of the chip based on a first comparison result of the real-time computing power ratio with a reference computing power ratio of the chip, a second comparison result of the real-time temperature with a reference temperature of the chip, and a third comparison result of the real-time voltage with a reference voltage of the chip, wherein the reference computing power ratio, the reference temperature, and the reference voltage are determined when the blockchain server undergoes a frequency rising phase after start-up and enters a working status. When an exception occurs in the chip, timely and appropriate response can improve stability of the blockchain server.

Chip frequency control method and apparatus, blockchain server, and storage medium

The present disclosure relates to a D flip-flop having a multiplexer function, including: a first transmission gate whose data input end is configured to receive a first data signal and whose clock input end is configured to receive a first clock signal; a second transmission gate whose data input end is configured to receive a second data signal and whose clock input end is configured to receive a second clock signal; an inverted latch unit whose data input end is connected to an output end of the first transmission gate and an output end of the second transmission gate and whose clock input end is configured to receive a third clock signal; and an inverter whose input end is connected to an output end of the inverted latch unit and whose output end provides an output of the D flip-flop.

D flip-flop having multiplexer function

A dynamic D flip-flop with an inverted output involves an input end () used for receiving input data; an output end () used for providing output data to respond to the input data; a clock signal end () used for receiving a clock signal; a first latch () used for latching the input data from the input end () and performing inverting transmission on the input data under the control of the clock signal; a second latch () used for latching data from the first latch () and performing inverting transmission on the data latched by the first latch () under the control of the clock signal; and an inverter () used for performing inverting output on the data received from the second latch (), the first latch (), the second latch (), and the inverter () being sequentially connected in series between the input end and the output end.

Dynamic D flip-flop with an inverted output

A computing device and a computing system are provided. The computing device comprises: a plurality of computing modules; and serial communication paths between/among the plurality of computing modules. Each computing module comprises: an internal circuit for performing an operation on a signal received from a corresponding serial communication path; and an extension circuit for receiving a signal from the internal circuit as an input signal. The extension circuit comprises: a delay module for delaying the input signal, the delay module comprising one or more delay units; one or more extension select modules for selectively performing a level extension on the input signal through the signal delayed by corresponding one or more delay units to generate one or more respective level-extended signals; and an output module for outputting one or more of the one or more level-extended signals.

Computing device and computing system

The present disclosure relates to clock circuits, computing chips, hash boards and data processing devices. A clock circuit comprises M stages of clock drive circuits that are connected in series, M being an integer that is no less than 2, wherein N inverters connected in series are arranged between an input port and an output port of each stage of the M stages of clock drive circuits, N being an odd number that is no less than 3. The clock circuit may provide clock signals with excellent performance.

Clock circuits, computing chips, hash boards and data processing devices

A D flip-flop, a processor including the D flip-flop, and a computing apparatus. A D flip-flop is provided, including: an input stage configured to receive a flip-flop input; an output stage configured to output a flip-flop output; an intermediate node disposed between an output of the input stage and an input of the output stage, where the output stage is configured to receive a signal at the intermediate node as an input; an intermediate stage configured to receive the output of the input stage and provide the output to the intermediate node; and a feedback stage configured to receive the flip-flop output and provide a feedback to the intermediate node, where the feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state.

D flip-flop, processor including the d flip-flop, and computing apparatus

An electronic device includes an arithmetic unit layer and a power supply. The arithmetic unit layer comprises at least one arithmetic unit. Each arithmetic unit comprises a first housing in a shape of cuboid. A first side direction of the first housing extends in a first direction. The first housing is provided with first and second openings at both ends in the first side direction thereof to form a coolant passage extending in the first direction. The power supply is stacked with arithmetic unit layer in a second or a third direction. A first side direction of the power supply is aligned with the first side direction of each arithmetic unit. The power supply is provided with third and fourth openings at both ends in the first side direction thereof to form a coolant passage extending in the first side direction of the power supply.

Electronic device and liquid cooling apparatus for electronic device

The present disclosure relates to a latch, a processor including the latch, and a computing apparatus. A latch with an inverted output is provided, including: an input stage configured to receive a latch input; an output stage configured to output a latch output; an intermediate node disposed between an output of the input stage and an input of the output stage, wherein the output stage is configured to receive a signal at the intermediate node as an input; and a feedback stage configured to receive the latch output and provide a feedback to the intermediate node, wherein feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state, wherein the latch output is inverted from the latch input.

Latch, processor including latch, and computing apparatus

Disclosed is a method for determining configuration parameters of a data processing device, including: operating the data processing device by using configuration parameters, which are universal optimization configuration parameters obtained according to a universal operating parameter model; during the operating process, changing the configuration parameters to obtain a dedicated operating parameter data set, which includes a plurality of groups of operating parameters, each of which includes configuration parameters and capability parameters of the data processing device when the data processing device is operating under the configuration parameters; executing model training by using the dedicated operating parameter data set to obtain a dedicated operating parameter model; and obtaining optimal configuration parameters according to the dedicated operating parameter model, and operating the data processing device according to the optimal configuration parameters, where the optimal configuration parameters are configuration parameters corresponding to optimal capability parameters in the dedicated operating parameter data set.

Method for determining configuration parameters of data processing device, electronic device and storage medium

A data processing device and a data processing system are provided. The data processing device includes a housing, which is thermally conductive and defines a sealed accommodating cavity; a hashboard, which is arranged in the accommodating cavity and is in fixed connection to the housing; a control board, which is in communicative connection to the hashboard; and a power supply module, which is in electrical connection to the hashboard.

Data processing device and data processing system

This disclosure relates to a pipeline clock driving circuit, a computing chip, a hashboard and a computing device. A pipeline clock driving circuit provides a pulse clock signal to a pipeline comprising multiple operation stages. The pipeline clock driving circuit includes multiple stages of clock driving circuits, each configured to provide the pulse clock signal to one corresponding operation stage; and a clock source coupled to an input of a first stage of clock driving circuit and configured to provide a basic clock signal. Inputs of other stages of clock driving circuits are coupled to outputs of previous stages of clock driving circuits. Each stage of clock driving circuit includes: a trigger; a delay module for outputting a delayed pulse signal to a next stage of clock driving circuit; and a combinational logic module for performing a combinational logic operation on the outputs to generate the pulse clock signal.

Pipeline clock driving circuit, computing chip, hashboard and computing device

A hashboard, a power supply system of a digital processing device and the digital processing device. The digital processing device comprises: a housing; N (≥2) hashboards and a control board both located inside the housing. Each hashboard comprises: a substrate; power positive and power negative terminals respectively mounted on the substrate and adapted to be connected to another hashboard in series; a communication interface mounted on the substrate; and computing chips mounted on the substrate. A signal transfer path of the computing chips has a chain configuration. The N hashboards are connected in series to form a series power supply configuration, a power positive terminal of a first hashboard in the series power supply configuration is connected to a positive terminal of a power supply, and a power negative terminal of a last hashboard in the series power supply configuration is connected to a negative terminal of the power supply.

Growing community of inventors

Shenzhen, China

Haifeng Guo