Cadence Design Systems, Inc.

Haifang Liao

Roland Ruehl

Krzysztof Antoni Kozminski

Eitan Cadouri

Xiaojun Wang

Mathew Koshy

Udayan Anand Gumaste

Tianhao Zhang

Li-Ling Ma

Kenneth Mednick

Xinming Tu

Xu Zhu

Mark A Snowden

Disclosed is a method and system for processing the tasks performed by an IC layout processing tool in parallel. In some approaches, the IC layout is divided into a plurality of layout portions and one or more of the layout portions are processed in parallel, where geometric select operations are performed in which data for different layout portions may be shared between different processing entities. One approach includes the following actions: select phase one operation for performing initial select actions within layout portions; distributed regioning action for local regioning; distributed regioning action for global regioning and binary select; count select aggregation for count-based select operations; and select phase two operations for combining results of selecting of internal shapes and interface shapes.

Method and system for parallel processing of IC design layouts

Disclosed is an improved method and system for processing the tasks performed by an EDA tool in parallel. The IC layout is divided into a plurality of layout windows and one or more of the layout windows are processed in parallel. Sampling of one or more windows may be performed to provide dynamic performance estimation.

Method and system for implementing parallel processing of electronic design automation tools

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San Jose, CA, United States of America

Haifang Liao