Intel Corporation

Cisco Technology, Inc.

Haichuan Tan

Daniel Christian Biederman

Howard Borchew

Senthil Arumugam

Glen J Anderson

Gabriel Arrobo Vidal

Chia-Hung Sophia Kuo

Sangeeta Ghangam Manepalli

Siew Wen Chin

Dan Biederman

Pradeep Sakhamoori

Systems and techniques for microservice latency reduction are described herein. A request may be received for execution of a microservice. An execution time may be calculated for the microservice. The execution time may be an estimation of time to complete execution of the microservice. A service level objective (SLO) may be identified. A processing unit of a computing node may be identified for execution of the microservice based on the precise execution time and the SLO. The microservice may be transmitted to the processing unit for instantiation.

Microservice latency reduction

Methods, apparatus, systems, and articles of manufacture for user-to-avatar mapping and adjustment are disclosed. An example apparatus includes processor circuitry to at least one of instantiate or execute the machine readable instructions to: determine a dissonance between a first orientation of a user in a real-world environment and a second orientation of an avatar in a virtual environment, the avatar corresponding to the user; determine an avatar adjustment value based on the dissonance; and apply the avatar adjustment value to the avatar model to change the second orientation.

User-to-avatar action mapping and adjustment

Disclosed, inter alia, is a Physical Layer Transceiver (PHY) with integrated time synchronization, such as, but not limited to, IEEE 1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems. The PHY includes circuitry to maintain a current time, and to trigger the storage of timestamps corresponding to received frames. Typically, in response to a request from an external device, the timestamps are retrieved from storage and are communicated to the external device. By moving the triggering of the storage of the timestamps by the PHY itself, rather than by a monitoring of the traffic between the PHY and the Media Access Controller (MAC), higher accuracy can typically be achieved.

Physical layer transceiver with integrated time synchronization

Disclosed are, inter alia, methods, apparatus, data structures, computer-readable media, mechanisms, and means for maintaining consistency among timestamp counters distributed among multiple devices. When timestamp counters are distributed among multiple physical devices, variances in their timestamp values can occur, such as, but not limited to those cause by variances among clocks in these different devices, different routing delays, different components, etc. These differences may be same, but still not allow high enough precision, especially as packet and processing rates continue to increase (which also causes clocking rates of devices to increase). One implementation distributes a time advance signal to each of these devices, which each device independently uses to determine when to advance its timestamp counter in response to its clock signal. These timestamps may be generated according to IEEE 1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems; and/or Physical Layer Transceivers (PHYs) may be disposed in each of the different physical devices.

Maintaining consistency among multiple timestamp counters distributed among multiple devices

Growing community of inventors

Santa Clara, CA, United States of America

Haichuan Tan