Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Skhynix Inc.

Sk Hynix Memory Solutions Inc.

Haibo Li

Xiying Costa

Dengtao Zhao

Kroum Stanimirov Stoev

Yongke Sun

Man Lung Mui

Fan Zhang

Masaaki Higashitani

Yu Cai

June Lee

Guirong Liang

Jui-Yao Yang

Roy E Scheuerlein

Mei-Man L Syu

Seung Yu

Chenfeng Zhang

Lingqi Zeng

Shi Yin

Sangsik Kim

Juhyeon Han

An apparatus of a memory system and an operating method thereof include: memory blocks, each of the memory blocks includes strings, each of the stings has flash cells and select gates thereon, wherein the select gates of each of the strings with a same index number in each of the memory blocks are connected with each other, in each of the memory blocks, the strings are divided into groups, each of the groups includes at least one string, and each of the groups has own read counts management thereof.

Memory system of 3D NAND flash and operating method thereof

Memory systems may include a memory including a plurality of memory blocks, and a controller suitable for, incrementing a first counter corresponding to a block of the plurality of blocks when the block is read, incrementing a second counter when the first counter reaches a predefined count number, determining an error count of the block when the second counter is incremented, and initiating a reclaim function when the error count exceeds an error threshold.

Adaptive read disturb reclaim policy

Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory.

Data retention flags in solid-state drives

Memory systems may include a memory including a plurality of wordlines, each wordline including a plurality of cells, and a controller suitable for obtaining an initial voltage threshold and a target state for each of the plurality of cells, applying a pulse based on a pulse value to the plurality of cells, and calculating at least one coupling effect to neighboring cells.

Modeling method of threshold voltage distributions

Systems and methods are provided to detect a developed bad word-line of a flash memory. Embodiments provide an improved Background media scan (BGMS) process that can predict at the end of a block read if a word-line will potentially become bad with the use of the flash memory. Accordingly, data from the potentially bad block can be recovered and the block can be retired. The embodiments can minimize the need for the expensive chip-kill method.

Detect developed bad blocks in non-volatile memory devices

Embodiments are directed to methods of classifying a flash memory block of N-level cells into sub-blocks. The N-level cells can store N bits of data. In some embodiments, the sub-blocks can represent one bit of each of the N-level cells. The sub-blocks can be selectively reclaimed in error-correction processes such as read disturb reclaim and retention refresh. Methods described can offer the advantage of reducing write amplification.

Selective data recycling in non-volatile memory

Systems and methods are disclosed for programming data in a non-volatile memory array are disclosed. A data storage device includes a non-volatile memory array including a plurality of non-volatile memory cells and a controller configured to receive a signal indicating a temperature of at least a portion of the data storage device. The controller determines a first offset program verify level associated with a first programming level based at least in part on the temperature and programs a first set of the memory cells of the non-volatile memory array using the first offset program verify level.

Temperature compensation management in solid-state memory

Memory systems may include a memory including a plurality of memory blocks and a controller. The controller calculates an effective read disturb based on both a direct neighbor read disturb count and a non-direct neighbor read disturb count. The controller selects a wordline with the largest effective read disturb for test read and deciding whether to reclaim the data of the block based on the errors on the wordline.

Read disturb reclaim policy

Systems and methods for data retention manager in a solid state storage system utilizing temperature measurement mechanisms are disclosed. Background data scanning can provide an efficient way to monitor data health and can be used to determine whether data refreshing is needed or to prevent data retention from degrading beyond error correction capabilities. In certain embodiments, data scanning may be performed as a background process regularly, for example, every month. However, effects of temperature on data retention may not be adequately accounted for using such methods. Certain embodiments disclosed herein provide a numerical integral method for taking account the system temperature by using the acceleration factor for data retention. Embodiments disclosed herein may provide for accurate handling of data retention in view of complex device temperature history.

Data retention monitoring using temperature history in solid state drives

An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.

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Sunnyvale, CA, United States of America

Haibo Li