Qualcomm Incorporated

Haibo Fei

Xiahan Zhou

Andrew Weil

Dongwon Seo

Matthew David Sienko

Chenling Huang

Gurkanwal Singh Sahota

Ankit Srivastava

Shahin Mehdizad Taleie

Ashok Swaminathan

Nitz Saputra

Jingxue Lu

Debesh Bhatta

Parisa Mahmoudidaryan

Jaswinder Singh

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) circuit. The DAC circuit generally includes: a decoder coupled to an input of the DAC circuit and current-steering cells coupled to an output of the decoder. Outputs of the current-steering cells may be coupled to a positive output node and a negative output node of the DAC circuit. The DAC circuit may also include an offset detection circuit including: a comparator having a first input and a second input selectively coupled to the positive output node and the negative output node; and a digital controller having an input coupled to an output of the comparator and an output coupled to the decoder. In some aspects, the DAC circuit includes one or more calibration DACs coupled to the offset detection circuit.

Current digital-to-analog converter (DAC) with direct-current (DC) offset correction

Certain aspects of the present disclosure generally relate to a digital-to-analog converter (DAC) circuit implemented with a dynamic stacked transistor architecture. The DAC circuit generally includes a first current-steering transistor and a second current-steering transistor. The DAC circuit may also include: a first stacked transistor coupled between the first current-steering transistor and a first output of the DAC circuit; a first switch coupled between a gate of the first stacked transistor and a bias voltage node; a second switch coupled between the gate of the first stacked transistor and a voltage rail; a second stacked transistor coupled between the second current-steering transistor and a second output of the DAC circuit; a third switch coupled between a gate of the second stacked transistor and the bias voltage node; and a fourth switch coupled between the gate of the second stacked transistor and the voltage rail.

Digital-to-analog converter (DAC) with dynamic stacked cascode switches

Methods and apparatus for controlling a power supply voltage for a switch driver in a digital-to-analog converter (DAC). An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a first switch coupled in series with the current source at a first node, and a switch driver having an output coupled to a control input of the first switch; and calibration circuitry having a first input coupled to a first DAC cell in the plurality of DAC cells and having an output coupled to at least one of the plurality of DAC cells, the calibration circuitry being configured to sense a voltage of the first node in the first DAC cell and to control the power supply voltage for the switch driver in the at least one of the plurality of DAC cells, based on the sensed voltage of the first node.

Digital-to-analog converter (DAC) with adaptive calibration scheme

Methods and apparatus for common-mode current removal in a digital-to-analog converter (DAC). An example DAC circuit generally includes a plurality of current-steering cells, a resistor ladder circuit coupled to the plurality of current-steering cells, a first current sink coupled between a shunt branch of the resistor ladder circuit and a reference potential node for the DAC circuit, and a second current sink coupled between a first output of the DAC circuit and the reference potential node.

Common-mode current removal scheme for digital-to-analog converters

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

Digital amplitude tracking current steering digital-to-analog converter

Certain aspects of the present disclosure are directed to a digital-to-analog converter (DAC) system. The DAC system generally includes a first current-steering DAC having a positive output, a negative output, and a bypass output; a common-mode (CM) path coupled between the positive and negative outputs; and a CM current compensation path coupled to the CM path.

Digital-to-analog converter (DAC) with common-mode correction

Disclosed is an amplifier circuit having an output stage that includes an H-bridge circuit. The H-bridge circuit includes sense resistors on one side of the circuit. A current detection circuit can produce an output indicative of current flow through a load based on voltages across the sense resistors.

Asymmetric H-bridge in a class D power amplifier

In an aspect of the disclosure, a class D power amplifier with an overcurrent protection (OCP) circuit is provided. The class D power amplifier includes a plurality of output transistors, and the OCP circuit is mirrored to at least one output transistor of the plurality of output transistors in a closed-loop feedback configuration for precisely controlling a sensing current of the OCP circuit with respect to an output current of the at least one output transistor. The class D power amplifier with the OCP circuit in the closed-loop feedback configuration mitigates a variation in a current threshold value for triggering interruption of the class D power amplifier.

Overcurrent protection for class D power amplifier

A class D power amplifier is provided. The class D power amplifier includes a class D driver circuit having a plurality of output transistors, at least one active clamp circuit coupled to at least one output transistor of the plurality of output transistors, and at least one filter bank circuit coupled to the at least one active clamp circuit for controlling a voltage of the at least one output transistor. Accordingly, a voltage across a drain node and source node (VDS), a voltage across a gate node and source node (VGS), and a voltage across the gate node and drain node (VGD) of the output transistors is reduced to increase reliability of the power amplifier while consuming less power and utilizing less die area.

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Haibo Fei