Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Hai Yang Zhang

Yan Wang

Cheng Zhang

Xin Jiang

Zhuo Fan Chen

Fang Yuan Xiao

Erhu Zheng

Min Da Hu

Er Hu Zheng

Yi Ying Zhang

Fangyuan Xiao

Zhe Zheng

Rong Yao Chang

Jing Yong Huang

A semiconductor device and fabrication method thereof are provided. The fabrication method include: providing a to-be-etched material layer; forming a plurality of discrete sacrificial layers on the to-be-etched material layer; forming first initial spacers on sidewalls of each of the discrete sacrificial layers. Each first initial spacer includes a first bottom region and a first top region on the first bottom region; removing the discrete sacrificial layers. The method further includes: removing the first top region of each first initial spacer to form a first spacer from each first bottom region; forming second spacers on sidewalls of each of the first spacers. Each second spacer includes a second bottom region and a second top region on the second bottom region; removing the first spacers; The method further includes: removing the second top regions by etching; and etching the to-be-etched material layer by using the second spacers as a mask.

Semiconductor device and fabrication method thereof

Semiconductor devices and fabrication methods are provided. A semiconductor device includes a substrate, a source and drain material layer formed on the substrate. The source and drain material layer contains a first trench there-through. The semiconductor device further includes a mask layer formed on the source and drain material layer containing a second trench there-through. The second trench has a cross-section area larger than the first trench and covers the first trench. The semiconductor device further includes a channel material layer conformally formed on a bottom and sidewalls of each of the first trench and the second trench and a gate structure conformally formed on the channel material layer, on the bottom and the sidewalls of each of the first trench and the second trench. The gate structure has a recess and the recess has a symmetrical step structure.

Semiconductor device

A semiconductor device and fabrication method thereof are provided. The fabrication method include: providing a to-be-etched material layer; forming a plurality of discrete sacrificial layers on the to-be-etched material layer; forming first initial spacers on sidewalls of each sacrificial layer, where each first initial spacer includes a first bottom region and a first top region on the first bottom region; removing the sacrificial layers; removing the first bottom region of the first initial spacer to form a first spacer from the first top region; forming second spacers on sidewalls of each first spacer; removing the first spacer; and etching the to-be-etched material layer by using the second spacers as an etch mask.

A semiconductor structure a base substrate and a sidewall spacer layer formed on the base substrate. The sidewall spacer layer includes a plurality of first sidewall spacer layers and a plurality of second sidewall spacer layers spaced apart from each other. At least one sidewall of a second sidewall spacer layer of the plurality of second sidewall spacer layers is formed on a first sidewall spacer layer of the plurality of first sidewall spacer layers. The plurality of first sidewall spacer layers has a thickness greater than the plurality of second sidewall spacer layers, based on a surface of the base substrate. The plurality of first sidewall spacer layers has a material structure different than the plurality of second sidewall spacer layers.

Semiconductor structures

A semiconductor device and a method for fabricating the semiconductor device are provided. The method includes forming a first composite structure, including a plurality of first composite layers, on a substrate, and forming a second composite structure, including a plurality of second composite layers on a surface portion of the first composite structure. The method also includes forming a first mask layer covering a sidewall of the second composite structure and a surface portion of the first composite structure and exposing at least another surface portion of the first composite structure. In addition, the method includes forming a second mask layer, on a surface portion of the second composite structure and spaced apart from the first mask layer by a first annular opening. Further, the method includes etching a top first layer of the first composite layers and a top first layer of the second composite layers.

Semiconductor device having composite structures and fabrication method thereof

A semiconductor device manufacturing method is presented. The method entails providing a semiconductor structure comprising a substrate, one or more semiconductor fins on the substrate, and a trench isolation structure around each semiconductor fin, wherein the trench isolation structure comprises a first component intersecting an extension direction of the semiconductor fin and a second component parallel with the extension direction; etching the trench isolation structure to expose a portion of the semiconductor fin; forming a patterned buffer layer on the semiconductor structure covering the second component and having an opening exposing the first component; forming an insulation layer in the opening, with upper surfaces of the insulation layer and the semiconductor fin substantially on the same horizontal level; and removing the buffer layer. This inventive concept reduces, if not eliminates, oxide loss in Single Diffusion Break (SDB) region.

Method for manufacturing semiconductor device that comprises a fin structure

An etching method and a fabrication method of semiconductor structures are provided. The etching method includes forming trenches in a to-be-etched structure, and forming a dielectric layer in the trenches. The etching method further includes etching the dielectric layer in the trenches by an etching process, and controlling at least an etching temperature of the etching process while a polymer is formed on side surface of the to-be-etched structure. During the etching process of the dielectric layer, the polymer undergoes a deposition stage and a removal stage. The deposition stage has a deposition rate of the polymer greater than an etch rate of the polymer, and the removal stage has the deposition rate of the polymer less than the etch rate of the polymer.

Etching method and fabrication method of semiconductor structures

Semiconductor devices and fabrication methods are provided. A fabrication method includes: forming a source and drain material layer over a substrate; forming a mask layer over the source and drain material layer and including a first trench exposing a portion of the source and drain material layer; forming a protective layer on sidewalls of the first trench; forming a second trench in the source and drain material layer using the mask layer and the protective layer as an etch mask; removing the protective layer after the second trench is formed; forming a channel material layer and a gate structure on the channel material layer after the protective layer is removed; and removing the mask layer after the channel material layer and the gate structure are formed. The channel material layer is on the sidewalls and the bottom of the first trench and the second trench.

A semiconductor device and its manufacturing method are presented, relating to semiconductor techniques. The manufacturing method includes: forming a multi-layer structure comprising one or more semiconductor structures on a substrate. The semiconductor structure is formed by: forming a first semiconductor layer; and forming a second semiconductor layer on the first semiconductor layer, wherein in at least one semiconductor structure, an ion implantation is conducted on a portion of the first semiconductor layer to form a doped region therein; etching the multi-layer structure to form a fin structure and a support structure on at least one side of the fin structure, with the support structure comprising at least a portion of the doped region; and removing the first semiconductor layer in the fin structure so that the second semiconductor layer becomes hanging over the substrate. This inventive concept ameliorates the bending issue of the second semiconductor layer.

Semiconductor device and manufacture thereof

A photomask manufacturing method relating to semiconductor technology is presented. The manufacturing method involves providing a substrate structure comprising an etch material layer, a first sacrificial layer on a portion of the etch material layer, and a photomask layer on an upper surface of the etch material layer and on an upper surface and a side surface of the first sacrificial layer; forming a second sacrificial layer covering the photomask layer on the etch material layer and on the side surface of the first sacrificial layer; etching the photomask layer not covered by the second sacrificial layer to expose the first sacrificial layer; removing the first sacrificial layer and the second sacrificial layer; and removing the photomask layer on the etch material layer. This photomask manufacturing method offers a photomask of better symmetricity than those from conventional methods.

Photomask manufacturing method

Semiconductor device and fabrication method are provided. The method includes: providing a base substrate with a bottom metallic layer in the base substrate and a dielectric layer on the base substrate; forming interconnect openings through the dielectric layer and exposing the bottom metallic layer, where each interconnect openings includes a contacting hole and a groove on the contacting hole; forming a first conducting layer in the contacting hole, where the first conducting layer is made of a material having a first conductivity along a direction from the bottom metallic layer to a top surface of the first conducting layer; and after forming the first conducting layer, forming a second conducting layer in the groove, where the second conducting layer is made of a material having a second conductivity along a direction parallel to the top surface of the base substrate and the first conductivity is greater than the second conductivity.

A semiconductor device includes an active region having a doped region, a first contact member on the doped region, gate structures including a first gate structure having a first gate and a second gate structure having a second gate, the first and second gate structures being adjacent to each other and on opposite sides of the first contact member, an interlayer dielectric layer on the active region and surrounding the first and second gate structures, and the first contact member, a first insulator layer on a portion of the interlayer dielectric layer, a first contact on an upper surface of the first gate and a second contact on an upper surface of the second gate, and a second insulator layer surrounding the first and second contacts each having an upper surface lower than an upper surface of the second insulator layer.

FinFET device

Semiconductor structures and fabrication methods thereof are provided. An exemplary fabrication method includes providing a semiconductor substrate having a first region, a second region and an isolation region between the first region and the second region; forming a plurality of first fins on the semiconductor substrate in the first region and a plurality of second fins on the semiconductor substrate in the second region; forming an isolation structure, covering portions of side surfaces of the first fins and the second fins and with a top surface below the top surfaces of the first fins and the second fins, over the semiconductor substrate; and forming an isolation layer over the isolation structure in the isolation region and with a top surface coplanar or above the top surfaces of the first fins and the second fins.

Semiconductor structure and fabrication method thereof

A method for manufacturing a semiconductor device includes providing a substrate structure including a substrate, semiconductor fins extending in a first direction on the substrate, a hardmask layer on the semiconductor fins, and an isolation region surrounding the semiconductor fins and having an upper surface flush with the hardmask layer, the isolation region including a first region on a side of the semiconductor fins in the first direction and a second region on a side of the semiconductor fins in a second direction different from the first direction. The method also includes removing the hardmask layer, etching a portion of the first region above the semiconductor fins, forming a mask layer on the semiconductor fins and a remaining first region, etching the second region such that an upper surface of the remaining second region is lower than an upper surface of the semiconductor fins, and removing the mask layer.

Fin cut process and fin structure

The present disclosure relates to the field of semiconductor technologies, and discloses a method for manufacturing a semiconductor apparatus. An implementation of the method may include: providing a substrate structure; depositing a dummy gate material layer on the substrate structure; performing planarization processing on the dummy gate material layer; after the planarization processing, performing, according to surface roughness of the dummy gate material layer, first etching on the dummy gate material layer by using a fluorine-containing gas; after the first etching, forming a fluorine-containing polymer layer on the dummy gate material layer; and performing second etching on the substrate structure on which the fluorine-containing polymer layer is formed, to remove the fluorine-containing polymer layer, where the second etching includes etching a surface of the dummy gate material layer. The method of the present invention improves surface smoothness and thickness uniformity of the dummy gate material layer.

Growing community of inventors

Shanghai, China

Hai Yang Zhang