Fairchild Semiconductor Corporation

Vitesse Semiconductor Corporation

Halo Microelectronics International

Finisar Corporation

Halo Microelectronics Co., Ltd.

Hai Tao

Ion E Opris

Shungneng Lee

Sudeep Bhoja

John S Wang

Lijie Zhao

Shanthi Pavan

Kien Chan Vi

Rui Liu

Derek Keith Shaeffer

Dong Sheng Li

Zhibo Tao

Liang Zhao

Chih-Hsien Hsieh

Kai-Fang Wei

Shuang Han

Jun Fan

Maodeng Li

Michelle Lee

An apparatus includes a plurality of binary weighted capacitors coupled between a first input terminal of a comparator and a plurality of signal buses, wherein the plurality of binary weighted capacitors has a binary weight increasing by two times from a first capacitor to an (N&#x2212;K)th capacitor, and a constant binary weight from the (N&#x2212;K)th capacitor to a (N&#x2212;K&#x2212;2+2)th capacitor, an offset voltage generator configured to generate a digitally controlled offset voltage having 2steps fed into a second input terminal of the comparator, and a successive approximation logic block configured to receive an output signal of the comparator, and generate an N-bit control signal for controlling the plurality of binary weighted capacitors.

ADC apparatus and control method

A method of converting an analog input signal to a digital output signal includes adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-to-digital converter circuit, wherein the digitally controlled offset voltage has a periodic pattern including at least 2steps, each of which has a value equal to an integer multiplying 2of an analog voltage corresponding to a least significant bit (LSB) of an N-bit digital signal, operating the successive approximation analog-to-digital converter circuit to sequentially generate at least a 2number of N-bit digital signals based on the at least 2steps of the digitally controlled offset voltage, summing the at least the 2number of N-bit digital signals to obtain a summing result, and dividing the summing result through a divider block to obtain a digital signal having (N+K) bits.

A control circuit is configured to control a flyback circuit comprising a primary-side switch, a secondary-side rectifier and a transformer. The control circuit comprises a feedback control circuit configured to generate a secondary-side control signal based on a current ripple signal of the transformer, and at least one of a direct-current component of an output voltage signal and a direct-current component of an output current signal of a secondary side of the flyback circuit, wherein the secondary-side control signal is configured to control a turn-off of the secondary-side rectifier, an isolated transmission circuit coupled to the feedback control circuit and configured to generate a first primary-side control signal based on the secondary-side control signal, and a primary control circuit coupled to the isolated transmission circuit and configured to control a turn-on of the primary-side switch in response to receiving the first primary-side control signal.

Control circuit of flyback circuit

An apparatus includes a first group of switches connected in series, a second group of switches connected in series, a first flying capacitor between a first common node and a third common node of the first group of switches, a second flying capacitor between a first common node and a third common node of the second group of switches, wherein the first group of switches and the second group of switches are configured such that the apparatus operates in one of three operating modes including a bypass operating mode, a hybrid operating mode and a boost/buck operating mode.

Power conversion circuit, power conversion system and power chip

This document provides apparatus and methods for cancelation of quadrature error from a micro-electromechanical system (MEMS) device, such as a MEMS gyroscope. In certain examples, a quadrature correction apparatus can include a drive charge-to-voltage (C2V) converter configured to provide drive information of a proof mass of a MEMS gyroscope, a sense C2V converter configured to provide sense information of the proof mass, a phase-shift module configured to provide phase shift information of the drive information, a drive demodulator configured to receive the drive information and the phase shift information and to provide demodulated drive information, a sense demodulator configured to receive the sense information and the phase shift information and to provide demodulated sense information, and wherein the quadrature correction apparatus is configured to provide corrected sense information using the demodulated drive information and the demodulated sense information.

MEMS device quadrature shift cancellation

This application discusses simplified interface circuits for a gyroscope. In an example, an interface can include an automatic gain control (AGC) circuit configured to couple to driver for a proof mass of a gyroscope sensor and to drive the proof-mass to oscillate at a predefined oscillation amplitude, and a phase-locked loop (PLL) configured to receive sensed oscillation information from the proof-mass and to provide at least a first phase signal synchronized with a sinusoidal waveform of the sensed oscillation information.

Apparatus and methods for PLL-based gyroscope gain control, quadrature cancellation and demodulation

In certain examples, a quadrature cancellation apparatus can include a drive charge amplifier configured to couple to a proof mass of a MEMS device and to provide oscillation motion information, a first sense charge amplifier configured to couple to the proof mass and to provide first sense information of a first movement of the MEMS device, a first programmable amplifier configured to receive the oscillation motion information and provide amplified oscillation motion information, a first summer configured to cancel quadrature error of the first sense information using the first sense information and the amplified oscillation motion information to provide quadrature-corrected first sense information, a phase shifter configured to receive the oscillation motion information and to provide carrier information, and a first multiplier configured to provide demodulated first sense information using the quadrature-corrected first sense information and the carrier information.

MEMS quadrature cancellation and signal demodulation

This document discusses, among other things, apparatus and methods for digital automatic gain control for driving a MEMS device, such as a proof mass. In an example, an apparatus can include a driver configured to oscillate a proof mass of a MEMS device, a charge-to-voltage (C2V) converter configured to provide oscillation information of the proof mass, an analog-to-digital converter (ADC) configured to provide a digital representation of the oscillation information, and a digital, automatic gain control circuit to provide oscillation amplitude error information using a comparison of the oscillation information to target amplitude information, and to provide a digital drive command signal using an amplified representation of the oscillation amplitude error information.

MEMS device automatic-gain control loop for mechanical amplitude drive

This document discusses, among other things, apparatus and methods for a front-end charge amplifier. In certain examples, a front-end charge amplifier for a microelectromechanical system (MEMS) device can include a charge amplifier configured to couple to the MEMS device and to provide sense information of a proof mass of the MEMS device, a feedback circuit configured to receive the sense information and to provide feedback to an input of the charge amplifier, and wherein the charge amplifier includes a transfer function having a first pole at a first frequency, a second pole at a second frequency, and one zero at a third frequency.

MEMS device front-end charge amplifier

In an example, a driver for a micro-electro-mechanical-system (MEMS) device can include a first input configured to receive a first command signal including an oscillatory command signal, a second input configured to receive a second command signal including a bias command signal, and an amplifier configured to receive a high voltage supply, to provide, to the MEMS device, a closed-loop output signal responsive to both the first command signal and the second command signal in a first state, and to provide an open loop output signal configured to substantially span a voltage range of the high voltage supply in a second state.

Micro-electro-mechanical-system (MEMS) driver

Methods, apparatuses, and systems are presented for performing adaptive equalization involving receiving a signal originating from a channel associated with inter-symbol interference, filtering the signal using a filter having a plurality of adjustable tap weights to produce a filtered signal, and adaptively updating each of the plurality of adjustable tap weights to a new value to reduce effects of inter-symbol interference, wherein each of the plurality of adjustable tap weights is adaptively updated to take into account a constraint relating to a measure of error in the filtered signal and a constraint relating to group delay associated with the filter. Each of the plurality of adjustable tap weights may be adaptively updated to drive group delay associated with the filter toward a target group delay.

Adaptive equalization with group delay

In a general aspect, an apparatus can include a first switch configured to be coupled to a power source and configured to switch in response to an edge of a control signal. The apparatus can include delay circuit can be configured to produce a delay signal that has an edge corresponding to the edge of the control signal, the edge of the delay signal being offset from the edge of the control signal. The apparatus can also include a second switch can be configured to be coupled to the power source in parallel with the first switch and configured to switch in response to the edge of the delay signal, the second switch having a size smaller than a size of the first switch.

Multiple switches and a delay circuit

In one general aspect, an apparatus can include a first voltage detect circuit configured to produce an output signal at a first power supply voltage, and configured to be in a non-monitoring state at a second power supply voltage greater than the first power supply voltage. The apparatus can include a second voltage detect circuit configured to change from a non-monitoring state to a monitoring state and configured to produce an output signal at a third power supply voltage between the first power supply voltage and the second power supply voltage. The apparatus can also include a combination circuit configured to produce a power-on-reset signal based on a logical combination of the output signal produced by the first voltage detect circuit and the output signal produced by the second voltage detect circuit.

Low power power-on-reset (POR) circuit

A method and apparatus for data multiplexing is capable of high-speed operation with acceptable timing margins and has reduced sensitivity to supply voltage, temperature, manufacturing and other variations. One implementation relates to a data multiplexer that has no significant speed limitation associated with the clock-to-data delay of data latches, flip-flops, etc. In one implementation, clock-to-data delay is compensated for by introducing a delay-compensator in the clock line that drives a selector stage of the multiplexer. In one such implementation, a timing relationship is established between clock and data waveforms by timing the data waveforms with a first in-phase clock and operating the delay-compensated selector clock line with a second clock, which is delayed with respect to the first clock. The second clock can have a quadrature-phase delay with respect to the in-phase clock.

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Sunnyvale, CA, United States of America

Hai Tao